Lines Matching defs:cd
380 const struct igma_chip *cd = &sc->sc_chip;
381 const struct igma_chip_ops *co = cd->ops;
382 int pipe = cd->use_pipe;
385 r = co->read_reg(cd, PIPE_HTOTAL(pipe));
387 r = co->read_reg(cd, PIPE_VTOTAL(pipe));
395 r = co->read_reg(cd, PF_WINSZ(pipe));
411 const struct igma_chip *cd = &sc->sc_chip;
412 const struct igma_chip_ops *co = cd->ops;
413 int pipe = cd->use_pipe;
420 b = co->read_vga(cd, 0x01);
421 co->write_vga(cd, 0x01, b | 0x20);
424 r = co->read_reg(cd, sc->sc_chip.vga_cntrl);
425 co->write_reg(cd, sc->sc_chip.vga_cntrl, r | VGA_CNTRL_DISABLE);
431 co->write_reg(cd, PF_WINPOS(pipe),
433 co->write_reg(cd, PF_WINSZ(pipe),
437 co->write_reg(cd, PIPE_SRCSZ(pipe),
441 co->write_reg(cd, PIPE_CONF(pipe),
445 r = co->read_reg(cd, PRI_CTRL(pipe));
448 co->write_reg(cd, PRI_CTRL(pipe), r | cd->pri_cntrl);
449 co->write_reg(cd, PRI_LINOFF(pipe), 0);
450 co->write_reg(cd, PRI_STRIDE(pipe), sc->sc_stride);
451 co->write_reg(cd, PRI_SURF(pipe), 0);
452 co->write_reg(cd, PRI_TILEOFF(pipe), 0);
454 if (cd->quirks & IGMA_PLANESTART_QUIRK)
457 if (cd->quirks & IGMA_PFITDISABLE_QUIRK)
461 co->write_reg(cd, PRI_CTRL(pipe), 0 | cd->pri_cntrl);
462 co->write_reg(cd, PRI_LINOFF(pipe), 0);
463 co->write_reg(cd, PRI_STRIDE(pipe), 2560);
464 co->write_reg(cd, PRI_SURF(pipe), 0);
465 co->write_reg(cd, PRI_TILEOFF(pipe), 0);
468 co->write_reg(cd, PIPE_SRCSZ(pipe),
472 co->write_reg(cd, PIPE_CONF(pipe), 0);
475 if ((co->read_reg(cd, PIPE_CONF(pipe)) & PIPE_CONF_STATE) == 0)
480 r = co->read_reg(cd, 0x42000);
481 co->write_reg(cd, 0x42000, (r & 0x1fffffff) | 0xa0000000);
482 r = co->read_reg(cd, 0x42004);
483 co->write_reg(cd, 0x42004, (r & 0xfbffffff) | 0x00000000);
486 co->write_reg(cd, PF_WINPOS(pipe),
488 co->write_reg(cd, PF_WINSZ(pipe),
492 r = co->read_reg(cd, sc->sc_chip.vga_cntrl);
493 co->write_reg(cd, sc->sc_chip.vga_cntrl, r & ~VGA_CNTRL_DISABLE);
496 b = co->read_vga(cd, 0x01);
497 co->write_vga(cd, 0x01, b & ~0x20);
503 co->write_reg(cd, PIPE_CONF(pipe),
511 const struct igma_chip *cd = &sc->sc_chip;
512 const struct igma_chip_ops *co = cd->ops;
513 int pipe = cd->use_pipe;
517 fwbcl = co->read_reg(cd, FW_BLC_SELF);
518 co->write_reg(cd, FW_BLC_SELF, fwbcl & ~FW_BLC_SELF_EN);
520 cntrl = co->read_reg(cd, CUR_CNTR(pipe));
521 co->write_reg(cd, CUR_CNTR(pipe), 1<<5 | 0x07);
526 co->write_reg(cd, CUR_CNTR(pipe), cntrl);
527 co->write_reg(cd, CUR_BASE(pipe),
528 co->read_reg(cd, CUR_BASE(pipe)));
530 co->write_reg(cd, FW_BLC_SELF, fwbcl);
536 const struct igma_chip *cd = &sc->sc_chip;
537 const struct igma_chip_ops *co = cd->ops;
541 r = co->read_reg(cd, PF_CTRL_I965);
542 co->write_reg(cd, PF_CTRL_I965, r & ~PF_ENABLE);
548 const struct igma_chip *cd = &sc->sc_chip;
549 const struct igma_chip_ops *co = cd->ops;
552 r = co->read_reg(cd, cd->backlight_cntrl);
555 r = co->read_reg(cd, RAWCLK_FREQ);
567 const struct igma_chip *cd = &sc->sc_chip;
568 const struct igma_chip_ops *co = cd->ops;
571 r = co->read_reg(cd, cd->backlight_cntrl);
579 const struct igma_chip *cd = &sc->sc_chip;
580 const struct igma_chip_ops *co = cd->ops;
583 r = co->read_reg(cd, cd->backlight_cntrl);
587 co->write_reg(cd, cd->backlight_cntrl,
Indexes created Sun Sep 28 07:09:56 GMT 2025