Lines Matching refs:co
378 const struct igma_chip_ops *co = cd->ops;
382 r = co->read_reg(cd, PIPE_HTOTAL(pipe));
384 r = co->read_reg(cd, PIPE_VTOTAL(pipe));
392 r = co->read_reg(cd, PF_WINSZ(pipe));
409 const struct igma_chip_ops *co = cd->ops;
417 b = co->read_vga(cd, 0x01);
418 co->write_vga(cd, 0x01, b | 0x20);
421 r = co->read_reg(cd, sc->sc_chip.vga_cntrl);
422 co->write_reg(cd, sc->sc_chip.vga_cntrl, r | VGA_CNTRL_DISABLE);
428 co->write_reg(cd, PF_WINPOS(pipe),
430 co->write_reg(cd, PF_WINSZ(pipe),
434 co->write_reg(cd, PIPE_SRCSZ(pipe),
438 co->write_reg(cd, PIPE_CONF(pipe),
442 r = co->read_reg(cd, PRI_CTRL(pipe));
445 co->write_reg(cd, PRI_CTRL(pipe), r | cd->pri_cntrl);
446 co->write_reg(cd, PRI_LINOFF(pipe), 0);
447 co->write_reg(cd, PRI_STRIDE(pipe), sc->sc_stride);
448 co->write_reg(cd, PRI_SURF(pipe), 0);
449 co->write_reg(cd, PRI_TILEOFF(pipe), 0);
458 co->write_reg(cd, PRI_CTRL(pipe), 0 | cd->pri_cntrl);
459 co->write_reg(cd, PRI_LINOFF(pipe), 0);
460 co->write_reg(cd, PRI_STRIDE(pipe), 2560);
461 co->write_reg(cd, PRI_SURF(pipe), 0);
462 co->write_reg(cd, PRI_TILEOFF(pipe), 0);
465 co->write_reg(cd, PIPE_SRCSZ(pipe),
469 co->write_reg(cd, PIPE_CONF(pipe), 0);
472 if ((co->read_reg(cd, PIPE_CONF(pipe)) & PIPE_CONF_STATE) == 0)
477 r = co->read_reg(cd, 0x42000);
478 co->write_reg(cd, 0x42000, (r & 0x1fffffff) | 0xa0000000);
479 r = co->read_reg(cd, 0x42004);
480 co->write_reg(cd, 0x42004, (r & 0xfbffffff) | 0x00000000);
483 co->write_reg(cd, PF_WINPOS(pipe),
485 co->write_reg(cd, PF_WINSZ(pipe),
489 r = co->read_reg(cd, sc->sc_chip.vga_cntrl);
490 co->write_reg(cd, sc->sc_chip.vga_cntrl, r & ~VGA_CNTRL_DISABLE);
493 b = co->read_vga(cd, 0x01);
494 co->write_vga(cd, 0x01, b & ~0x20);
500 co->write_reg(cd, PIPE_CONF(pipe),
509 const struct igma_chip_ops *co = cd->ops;
514 fwbcl = co->read_reg(cd, FW_BLC_SELF);
515 co->write_reg(cd, FW_BLC_SELF, fwbcl & ~FW_BLC_SELF_EN);
517 cntrl = co->read_reg(cd, CUR_CNTR(pipe));
518 co->write_reg(cd, CUR_CNTR(pipe), 1<<5 | 0x07);
523 co->write_reg(cd, CUR_CNTR(pipe), cntrl);
524 co->write_reg(cd, CUR_BASE(pipe),
525 co->read_reg(cd, CUR_BASE(pipe)));
527 co->write_reg(cd, FW_BLC_SELF, fwbcl);
534 const struct igma_chip_ops *co = cd->ops;
538 r = co->read_reg(cd, PF_CTRL_I965);
539 co->write_reg(cd, PF_CTRL_I965, r & ~PF_ENABLE);
546 const struct igma_chip_ops *co = cd->ops;
549 r = co->read_reg(cd, cd->backlight_cntrl);
552 r = co->read_reg(cd, RAWCLK_FREQ);
565 const struct igma_chip_ops *co = cd->ops;
568 r = co->read_reg(cd, cd->backlight_cntrl);
577 const struct igma_chip_ops *co = cd->ops;
580 r = co->read_reg(cd, cd->backlight_cntrl);
584 co->write_reg(cd, cd->backlight_cntrl,
Indexes created Wed Oct 29 18:09:52 GMT 2025