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Lines Matching refs:sc_wdcdev

90 	sc->sc_wdcdev.sc_atac.atac_dev = self;
111 	    device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cfg & IT_CFG_MASK,
117 	aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
122 	sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
125 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
126 		sc->sc_wdcdev.irqack = pciide_irqack;
128 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
129 	sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
130 	sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
132 	sc->sc_wdcdev.sc_atac.atac_set_modes = ite_setup_channel;
133 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
134 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
135 	sc->sc_wdcdev.wdc_maxdrives = 2;
137 	wdc_allocate_regs(&sc->sc_wdcdev);
146 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; channel++) {
158 	    device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cfg & IT_CFG_MASK,
178 	    device_xname(sc->sc_wdcdev.sc_atac.atac_dev),
207 				    device_xname(sc->sc_wdcdev.sc_atac.atac_dev),
252 	    device_xname(sc->sc_wdcdev.sc_atac.atac_dev), tim), DEBUG_PROBE);