Cross Reference: /src/sys/dev/pci/ixgbe/if

Lines Matching defs:hw
97 ixgbe_send_vf_msg(struct ixgbe_hw *hw, struct ixgbe_vf *vf, u32 msg)
102 	hw->mbx.ops[vf->pool].write(hw, &msg, 1, vf->pool);
109 	ixgbe_send_vf_msg(&sc->hw, vf, msg | IXGBE_VT_MSGTYPE_SUCCESS);
116 	ixgbe_send_vf_msg(&sc->hw, vf, msg | IXGBE_VT_MSGTYPE_FAILURE);
212 			ixgbe_send_vf_msg(&sc->hw, vf, IXGBE_PF_CONTROL_MSG);
221 	struct ixgbe_hw *hw;
224 	hw = &sc->hw;
228 	vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf->pool));
252 	IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf->pool), vmolr);
253 	IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf->pool), vmvir);
260 	struct ixgbe_hw *hw = &sc->hw;
262 	uint16_t mbx_size = hw->mbx.size;
268 		IXGBE_WRITE_REG_ARRAY(hw, IXGBE_PFMBMEM(vf_index), i, 0x0);
281 	if (sc->hw.mac.type != ixgbe_mac_82599EB)
326 	ixgbe_clear_rar(&sc->hw, vf->rar_index);
328 	ixgbe_toggle_txdctl(&sc->hw, IXGBE_VF_INDEX(vf->pool));
337 	struct ixgbe_hw *hw;
340 	hw = &sc->hw;
343 	vfte = IXGBE_READ_REG(hw, IXGBE_VFTE(vf_index));
345 	IXGBE_WRITE_REG(hw, IXGBE_VFTE(vf_index), vfte);
352 	struct ixgbe_hw *hw;
355 	hw = &sc->hw;
358 	vfre = IXGBE_READ_REG(hw, IXGBE_VFRE(vf_index));
363 	IXGBE_WRITE_REG(hw, IXGBE_VFRE(vf_index), vfre);
370 	struct ixgbe_hw *hw;
374 	hw = &sc->hw;
379 		ixgbe_set_rar(&sc->hw, vf->rar_index, vf->ether_addr,
392 	resp[3] = hw->mac.mc_filter_type;
393 	hw->mbx.ops.write(hw, resp, IXGBE_VF_PERMADDR_MSG_LEN, vf->pool);
417 	ixgbe_set_rar(&sc->hw, vf->rar_index, vf->ether_addr, vf->pool,
438 	vmolr = IXGBE_READ_REG(&sc->hw, IXGBE_VMOLR(vf->pool));
447 		mta_reg = IXGBE_READ_REG(&sc->hw, IXGBE_MTA(vec_reg));
449 		IXGBE_WRITE_REG(&sc->hw, IXGBE_MTA(vec_reg), mta_reg);
453 	IXGBE_WRITE_REG(&sc->hw, IXGBE_VMOLR(vf->pool), vmolr);
461 	struct ixgbe_hw *hw;
465 	hw = &sc->hw;
480 	ixgbe_set_vfta(hw, tag, vf->pool, enable, false);
488 	struct ixgbe_hw *hw;
491 	hw = &sc->hw;
517 	mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
523 		IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
561 	struct ixgbe_hw *hw;
565 	hw = &sc->hw;
584 	hw->mbx.ops.write(hw, resp, IXGBE_VF_GET_QUEUES_RESP_LEN, vf->pool);
591 	struct ixgbe_hw *hw;
595 	hw = &sc->hw;
597 	error = hw->mbx.ops[vf->pool].read(hw, msg, IXGBE_VFMAILBOX_SIZE,
648 	struct ixgbe_hw *hw;
654 	hw = &sc->hw;
662 		if (hw->mbx.ops[vf->pool].check_for_rst(hw, vf->pool) == 0)
665 		if (hw->mbx.ops[vf->pool].check_for_msg(hw, vf->pool) == 0)
668 		if (hw->mbx.ops[vf->pool].check_for_ack(hw, vf->pool) == 0)
719 	ixgbe_init_mbx_params_pf(&sc->hw);
741 	struct ixgbe_hw *hw;
746 	hw = &sc->hw;
752 	IXGBE_WRITE_REG(hw, IXGBE_VFRE(pf_reg), IXGBE_VF_BIT(sc->pool));
753 	IXGBE_WRITE_REG(hw, IXGBE_VFTE(pf_reg), IXGBE_VF_BIT(sc->pool));
759 	IXGBE_WRITE_REG(hw, IXGBE_VFRE(vf_reg), 0);
760 	IXGBE_WRITE_REG(hw, IXGBE_VFTE(vf_reg), 0);
762 	IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
775 	struct ixgbe_hw *hw;
780 	hw = &sc->hw;
786 	pfmbimr = IXGBE_READ_REG(hw, IXGBE_PFMBIMR(vf_index));
788 	IXGBE_WRITE_REG(hw, IXGBE_PFMBIMR(vf_index), pfmbimr);
795 		ixgbe_set_rar(&sc->hw, vf->rar_index,
802 	ixgbe_send_vf_msg(&sc->hw, vf, IXGBE_PF_CONTROL_MSG);
808 	struct ixgbe_hw *hw = &sc->hw;
819 	mrqc    = IXGBE_READ_REG(hw, IXGBE_MRQC);
820 	gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
821 	gpie    = IXGBE_READ_REG(hw, IXGBE_GPIE);
845 	IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
846 	IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
847 	IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
848 	IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
852 	IXGBE_WRITE_REG(hw, IXGBE_VFRE(vf_reg), IXGBE_VF_BIT(sc->pool));
853 	IXGBE_WRITE_REG(hw, IXGBE_VFTE(vf_reg), IXGBE_VF_BIT(sc->pool));
856 	IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
860 	IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
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