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Lines Matching defs:eicr

3155 	u32		eicr;
3170 	 * errata to read EICS instead of EICR to get interrupt cause.
3171 	 * At least, reading EICR clears lower 16bits of EIMS on 82598.
3173 	eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
3175 	eicr &= ~IXGBE_EICR_RTX_QUEUE;
3177 	IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
3179 	ixgbe_intr_admin_common(sc, eicr, &eims_disable);
3188 ixgbe_intr_admin_common(struct ixgbe_softc *sc, u32 eicr, u32 *eims_disable)
3195 	if (eicr & IXGBE_EICR_LSC) {
3215 		if ((eicr & eicr_mask)
3217 			&& (eicr & IXGBE_EICR_LSC))) {
3223 		    (eicr & IXGBE_EICR_GPI_SDP1_BY_MAC(hw))) {
3232 		    (eicr & IXGBE_EICR_FLOW_DIR)) {
3241 		if (eicr & IXGBE_EICR_ECC) {
3252 				if (!(eicr & IXGBE_EICR_GPI_SDP0_X550EM_a))
3267 				if (!(eicr & IXGBE_EICR_TS))
3286 		    (eicr & IXGBE_EICR_MAILBOX)) {
3294 		ixgbe_check_fan_failure(sc, eicr, true);
3298 	    (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
5301 	u32		eicr;
5309 	 * EICR.
5313 	/* Read and clear EICR */
5314 	eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
5316 	if (eicr == 0) {
5325 	    (eicr & IXGBE_EIMC_RTX_QUEUE) != 0) {
5349 	ixgbe_intr_admin_common(sc, eicr, &eims_disable);