Lines Matching refs:hw
54 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
57 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
58 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
60 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
62 static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw);
63 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
65 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
68 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
70 struct ixgbe_mac_info *mac = &hw->mac;
78 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
79 !ixgbe_mng_enabled(hw)) {
92 if (hw->phy.multispeed_fiber) {
98 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber_fixed)
102 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
103 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
104 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
105 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
115 * @hw: pointer to hardware structure
122 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
124 struct ixgbe_mac_info *mac = &hw->mac;
125 struct ixgbe_phy_info *phy = &hw->phy;
131 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {
133 hw->phy.qsfp_shared_i2c_bus = TRUE;
136 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
142 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
143 IXGBE_WRITE_FLUSH(hw);
149 ret_val = phy->ops.identify(hw);
154 ixgbe_init_mac_link_ops_82599(hw);
155 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
156 hw->phy.ops.reset = NULL;
159 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
166 switch (hw->phy.type) {
180 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
187 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
188 ixgbe_init_mac_link_ops_82599(hw);
190 hw->phy.ops.reset = NULL;
192 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
198 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
205 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
208 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
209 IXGBE_WRITE_FLUSH(hw);
210 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
215 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
219 msec_delay(hw->eeprom.semaphore_delay);
222 ret_val = hw->mac.ops.prot_autoc_write(hw,
223 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL,
239 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
241 msec_delay(hw->eeprom.semaphore_delay);
249 * @hw: pointer to hardware structure
257 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
263 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
264 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
272 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
278 * @hw: pointer to hardware structure
286 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
291 if (ixgbe_check_reset_blocked(hw))
298 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) {
299 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
307 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
308 ret_val = ixgbe_reset_pipeline_82599(hw);
315 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
322 * @hw: pointer to hardware structure
328 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
330 struct ixgbe_mac_info *mac = &hw->mac;
331 struct ixgbe_phy_info *phy = &hw->phy;
332 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
338 ixgbe_init_phy_ops_generic(hw);
339 ret_val = ixgbe_init_ops_generic(hw);
383 ixgbe_init_mac_link_ops_82599(hw);
391 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
393 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))
397 hw->mbx.ops[i].init_params = ixgbe_init_mbx_params_pf;
418 * @hw: pointer to hardware structure
424 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
435 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
436 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
437 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
438 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
439 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
440 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
451 if (hw->mac.orig_link_settings_stored)
452 autoc = hw->mac.orig_autoc;
454 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
511 if (hw->phy.multispeed_fiber) {
518 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp)
530 * @hw: pointer to hardware structure
534 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
541 switch (hw->phy.type) {
550 switch (hw->device_id) {
582 hw->phy.multispeed_fiber = TRUE;
594 * @hw: pointer to hardware structure
599 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
605 ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
607 if (!ixgbe_mng_present(hw) && !hw->wol_enabled &&
609 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
611 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
617 * @hw: pointer to hardware structure
623 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
637 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
638 status = hw->mac.ops.acquire_swfw_sync(hw,
647 ixgbe_reset_pipeline_82599(hw);
650 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
654 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
663 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
684 * @hw: pointer to hardware structure
690 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
692 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
695 if (ixgbe_check_reset_blocked(hw))
700 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
701 IXGBE_WRITE_FLUSH(hw);
707 * @hw: pointer to hardware structure
713 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
715 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
719 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
720 IXGBE_WRITE_FLUSH(hw);
726 * @hw: pointer to hardware structure
736 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
741 if (ixgbe_check_reset_blocked(hw))
744 if (hw->mac.autotry_restart) {
745 ixgbe_disable_tx_laser_multispeed_fiber(hw);
746 ixgbe_enable_tx_laser_multispeed_fiber(hw);
747 hw->mac.autotry_restart = FALSE;
753 * @hw: pointer to hardware structure
758 void ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw,
761 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
776 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
777 IXGBE_WRITE_FLUSH(hw);
782 * @hw: pointer to hardware structure
788 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
796 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
801 hw->phy.autoneg_advertised = 0;
804 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
807 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
810 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
820 hw->phy.smart_speed_active = FALSE;
822 status = ixgbe_setup_mac_link_82599(hw, speed,
837 status = ixgbe_check_link(hw, &link_speed, &link_up,
856 hw->phy.smart_speed_active = TRUE;
857 status = ixgbe_setup_mac_link_82599(hw, speed,
872 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
881 hw->phy.smart_speed_active = FALSE;
882 status = ixgbe_setup_mac_link_82599(hw, speed,
894 * @hw: pointer to hardware structure
900 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
907 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this current point in time */
910 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
919 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
926 ixgbe_disable_tx_laser(hw); /* For fiber */
927 ixgbe_set_phy_power(hw, false); /* For copper */
930 ixgbe_enable_tx_laser(hw); /* for Fiber */
931 ixgbe_set_phy_power(hw, true); /* For copper */
935 if (hw->mac.orig_link_settings_stored)
936 orig_autoc = hw->mac.orig_autoc;
952 (hw->phy.smart_speed_active == FALSE))
972 if (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel)
981 status = hw->mac.ops.prot_autoc_write(hw, autoc, FALSE);
993 IXGBE_READ_REG(hw, IXGBE_LINKS);
1016 * @hw: pointer to hardware structure
1022 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
1031 status = hw->phy.ops.setup_link_speed(hw, speed,
1034 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
1041 * @hw: pointer to hardware structure
1047 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
1060 status = hw->mac.ops.stop_adapter(hw);
1065 ixgbe_clear_tx_pending(hw);
1070 phy_status = hw->phy.ops.init(hw);
1076 if (hw->phy.sfp_setup_needed) {
1077 phy_status = hw->mac.ops.setup_sfp(hw);
1078 hw->phy.sfp_setup_needed = FALSE;
1085 if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL)
1086 hw->phy.ops.reset(hw);
1090 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;
1100 if (!hw->force_full_reset) {
1101 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE);
1106 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1107 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1108 IXGBE_WRITE_FLUSH(hw);
1113 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1128 * allow time for any pending HW events to complete.
1130 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1131 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1140 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1141 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1146 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1147 IXGBE_WRITE_FLUSH(hw);
1150 if (hw->mac.orig_link_settings_stored == FALSE) {
1151 hw->mac.orig_autoc = autoc;
1152 hw->mac.orig_autoc2 = autoc2;
1153 hw->mac.orig_link_settings_stored = TRUE;
1162 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) ||
1163 hw->wol_enabled)
1164 hw->mac.orig_autoc =
1165 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
1168 if (autoc != hw->mac.orig_autoc) {
1169 status = hw->mac.ops.prot_autoc_write(hw,
1170 hw->mac.orig_autoc,
1177 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1179 autoc2 |= (hw->mac.orig_autoc2 &
1181 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1186 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1193 hw->mac.num_rar_entries = 128;
1194 hw->mac.ops.init_rx_addrs(hw);
1197 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1200 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1202 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1204 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
1205 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1208 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
1212 hw->mac.num_rar_entries--;
1216 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1217 &hw->mac.wwpn_prefix);
1228 * @hw: pointer to hardware structure
1231 static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd)
1236 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1247 * @hw: pointer to hardware structure
1249 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1253 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1263 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1269 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1270 IXGBE_WRITE_FLUSH(hw);
1278 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1279 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1281 IXGBE_WRITE_FLUSH(hw);
1282 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1283 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1285 IXGBE_WRITE_FLUSH(hw);
1290 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1291 IXGBE_WRITE_FLUSH(hw);
1293 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1294 IXGBE_WRITE_FLUSH(hw);
1298 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1309 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1310 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1311 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1312 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1313 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1320 * @hw: pointer to hardware structure
1323 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1330 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1331 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1346 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1347 IXGBE_WRITE_FLUSH(hw);
1349 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1361 * @hw: pointer to hardware structure
1365 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1380 ixgbe_fdir_enable_82599(hw, fdirctrl);
1387 * @hw: pointer to hardware structure
1392 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
1419 ixgbe_fdir_enable_82599(hw, fdirctrl);
1426 * @hw: pointer to hardware structure
1429 void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue)
1435 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1440 if ((hw->mac.type == ixgbe_mac_X550) ||
1441 (hw->mac.type == ixgbe_mac_X550EM_x) ||
1442 (hw->mac.type == ixgbe_mac_X550EM_a))
1445 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1446 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1448 IXGBE_WRITE_FLUSH(hw);
1449 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1450 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1452 IXGBE_WRITE_FLUSH(hw);
1455 ixgbe_fdir_enable_82599(hw, fdirctrl);
1551 * @hw: pointer to hardware structure
1559 void ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1606 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1718 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1842 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m);
1848 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);
1849 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);
1850 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);
1851 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);
1852 switch (hw->mac.type) {
1856 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF);
1864 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1872 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1873 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1875 switch (hw->mac.type) {
1879 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
1886 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1888 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1890 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, 0xFFFFFFFF);
1895 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1908 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1910 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1912 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1916 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA,
1921 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA,
1928 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1935 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1948 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), addr_low);
1949 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), cloud_type);
1950 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.tni_vni);
1956 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1962 IXGBE_WRITE_FLUSH(hw);
1975 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1976 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1985 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1996 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1998 /* flush hash to HW */
1999 IXGBE_WRITE_FLUSH(hw);
2002 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
2004 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
2012 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
2013 IXGBE_WRITE_FLUSH(hw);
2014 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
2023 * @hw: pointer to hardware structure
2033 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
2075 /* program input mask into the HW */
2076 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode);
2084 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
2090 * @hw: pointer to hardware structure
2096 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
2102 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2104 IXGBE_WRITE_FLUSH(hw);
2106 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2114 * @hw: pointer to hardware structure
2120 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
2127 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2128 IXGBE_WRITE_FLUSH(hw);
2136 * @hw: pointer to hardware structure
2142 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2148 ret_val = ixgbe_start_hw_generic(hw);
2152 ixgbe_start_hw_gen2(hw);
2155 hw->mac.autotry_restart = TRUE;
2158 ret_val = ixgbe_verify_fw_version_82599(hw);
2165 * @hw: pointer to hardware structure
2168 * If PHY already detected, maintains current PHY type in hw struct,
2171 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2178 status = ixgbe_identify_phy_generic(hw);
2181 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
2184 status = ixgbe_identify_module_generic(hw);
2188 if (hw->phy.type == ixgbe_phy_unknown) {
2189 hw->phy.type = ixgbe_phy_none;
2194 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
2202 * @hw: pointer to hardware structure
2206 u64 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2209 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2210 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2218 hw->phy.ops.identify(hw);
2220 switch (hw->phy.type) {
2223 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2282 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2289 * @hw: pointer to hardware structure
2294 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2306 hw->mac.ops.disable_sec_rx_path(hw);
2309 ixgbe_enable_rx(hw);
2311 ixgbe_disable_rx(hw);
2313 hw->mac.ops.enable_sec_rx_path(hw);
2320 * @hw: pointer to hardware structure
2328 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2337 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2343 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) {
2353 if (hw->eeprom.ops.read(hw, (fw_offset +
2367 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2384 * @hw: pointer to hardware structure
2389 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2398 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2405 status = hw->eeprom.ops.read(hw, (fw_offset +
2414 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2430 * @hw: pointer to hardware structure
2437 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2440 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2451 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2454 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2465 * @hw: pointer to hardware structure
2471 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2474 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2485 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2487 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2495 * @hw: pointer to hardware structure
2500 static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2507 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2510 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2511 IXGBE_WRITE_FLUSH(hw);
2514 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2517 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
2522 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2537 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2538 IXGBE_WRITE_FLUSH(hw);
2545 * @hw: pointer to hardware structure
2553 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2562 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2564 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2566 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2567 IXGBE_WRITE_FLUSH(hw);
2570 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2586 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2590 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2592 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2594 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2595 IXGBE_WRITE_FLUSH(hw);
2603 * @hw: pointer to hardware structure
2611 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2620 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2622 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2624 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2625 IXGBE_WRITE_FLUSH(hw);
2628 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2644 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2648 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2650 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2652 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2653 IXGBE_WRITE_FLUSH(hw);
Indexes created Wed Oct 15 16:09:53 GMT 2025