Lines Matching refs:hw
47 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
48 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
49 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
50 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
51 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
52 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
53 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
54 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
55 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
56 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
57 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
58 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
63 * @hw: pointer to the hardware structure
68 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
72 status = ixgbe_clock_out_i2c_byte(hw, byte);
75 return ixgbe_get_i2c_ack(hw);
80 * @hw: pointer to the hardware structure
85 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
87 ixgbe_clock_in_i2c_byte(hw, byte);
89 return ixgbe_clock_out_i2c_bit(hw, FALSE);
109 * @hw: pointer to the hardware structure
117 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
120 u32 swfw_mask = hw->phy.phy_semaphore_mask;
133 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
135 ixgbe_i2c_start(hw);
137 if (ixgbe_out_i2c_byte_ack(hw, addr))
140 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
143 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
146 if (ixgbe_out_i2c_byte_ack(hw, csum))
149 ixgbe_i2c_start(hw);
151 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
154 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
157 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
160 ixgbe_clock_in_i2c_byte(hw, &csum_byte);
162 if (ixgbe_clock_out_i2c_bit(hw, FALSE))
164 ixgbe_i2c_stop(hw);
166 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
171 ixgbe_i2c_bus_clear(hw);
173 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
186 * @hw: pointer to the hardware structure
194 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
197 u32 swfw_mask = hw->phy.phy_semaphore_mask;
209 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
211 ixgbe_i2c_start(hw);
213 if (ixgbe_out_i2c_byte_ack(hw, addr))
216 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
219 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
222 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
225 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
228 if (ixgbe_out_i2c_byte_ack(hw, csum))
230 ixgbe_i2c_stop(hw);
232 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
236 ixgbe_i2c_bus_clear(hw);
238 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
251 * @hw: pointer to the hardware structure
255 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
257 struct ixgbe_phy_info *phy = &hw->phy;
289 * @hw: pointer to hardware structure
294 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
298 if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
304 if (ixgbe_get_phy_id(hw))
307 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
309 if (hw->phy.type == ixgbe_phy_unknown) {
310 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
315 hw->phy.type = ixgbe_phy_cu_unknown;
317 hw->phy.type = ixgbe_phy_generic;
325 * @hw: pointer to hardware structure
329 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
336 if (!hw->phy.phy_semaphore_mask) {
337 if (hw->bus.lan_id)
338 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
340 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
343 if (hw->phy.type != ixgbe_phy_unknown)
346 if (hw->phy.nw_mng_if_sel) {
347 phy_addr = (hw->phy.nw_mng_if_sel &
350 if (ixgbe_probe_phy(hw, phy_addr))
357 if (ixgbe_probe_phy(hw, phy_addr)) {
368 hw->phy.addr = 0;
375 * @hw: pointer to the hardware structure
382 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
389 if (hw->mac.type == ixgbe_mac_82598EB)
392 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
404 * @hw: pointer to hardware structure
408 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
415 hw->phy.addr = phy_addr;
416 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
429 * @hw: pointer to hardware structure
432 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
440 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
445 hw->phy.id = (u32)(phy_id_high << 16);
446 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
449 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
450 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
500 * @hw: pointer to hardware structure
502 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
510 if (hw->phy.type == ixgbe_phy_unknown)
511 status = ixgbe_identify_phy_generic(hw);
513 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
517 if (!hw->phy.reset_if_overtemp &&
518 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
522 if (ixgbe_check_reset_blocked(hw))
529 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
540 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
541 status = hw->phy.ops.read_reg(hw,
553 status = hw->phy.ops.read_reg(hw,
580 * @hw: pointer to hardware structure
585 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw
593 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
596 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
606 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
624 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
627 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
637 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
652 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
662 * @hw: pointer to hardware structure
667 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
671 u32 gssr = hw->phy.phy_semaphore_mask;
675 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
678 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
680 hw->mac.ops.release_swfw_sync(hw, gssr);
688 * @hw: pointer to hardware structure
693 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
699 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
704 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
707 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
717 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
733 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
736 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
746 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
762 * @hw: pointer to hardware structure
767 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
771 u32 gssr = hw->phy.phy_semaphore_mask;
775 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
776 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
778 hw->mac.ops.release_swfw_sync(hw, gssr);
788 * @hw: pointer to hardware structure
792 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
801 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
804 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
809 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
813 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
817 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
821 if (hw->mac.type == ixgbe_mac_X550) {
824 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
830 if ((hw->phy.autoneg_advertised &
838 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
842 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
847 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
853 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
857 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
861 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_100_FULL) {
865 hw->phy.ops.read_reg(hw, MDIO_PMAPMD_CTRL1, MDIO_MMD_PMAPMD,
869 hw->phy.ops.write_reg(hw, MDIO_PMAPMD_CTRL1,MDIO_MMD_PMAPMD,
873 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
878 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
882 if (ixgbe_check_reset_blocked(hw))
886 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
891 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
900 * @hw: pointer to hardware structure
904 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
916 hw->phy.autoneg_advertised = 0;
919 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
922 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
925 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
928 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
931 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
934 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
937 ixgbe_setup_phy_link(hw);
944 * @hw: pointer to hardware structure
949 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
954 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
961 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
963 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
965 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
967 switch (hw->mac.type) {
969 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
970 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
974 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
985 * @hw: pointer to hardware structure
989 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
998 if (!hw->phy.speeds_supported)
999 status = ixgbe_get_copper_speeds_supported(hw);
1001 *speed = hw->phy.speeds_supported;
1007 * @hw: pointer to hardware structure
1014 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1037 status = hw->phy.ops.read_reg(hw,
1058 * @hw: pointer to hardware structure
1062 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1071 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1075 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1080 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1083 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1090 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1095 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1098 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1105 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1110 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1113 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1119 if (ixgbe_check_reset_blocked(hw))
1123 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1128 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1136 * @hw: pointer to hardware structure
1139 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1146 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1155 * @hw: pointer to hardware structure
1158 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1165 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1174 * @hw: pointer to hardware structure
1176 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1188 if (ixgbe_check_reset_blocked(hw))
1191 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1195 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1200 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1214 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1219 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1225 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1240 ret_val = hw->eeprom.ops.read(hw, data_offset,
1246 ret_val = hw->eeprom.ops.read(hw, data_offset,
1250 hw->phy.ops.write_reg(hw, phy_offset,
1294 ixgbe_sfp_cage_full(struct ixgbe_hw *hw)
1299 KASSERT(hw->mac.type != ixgbe_mac_82598EB);
1301 if (hw->mac.type >= ixgbe_mac_X540)
1306 rv = IXGBE_READ_REG(hw, IXGBE_ESDP) & mask;
1307 if ((hw->quirks & IXGBE_QUIRK_MOD_ABS_INVERT) != 0)
1310 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1320 * @hw: pointer to hardware structure
1322 * Determines HW type and calls appropriate function.
1324 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1331 if (hw->mac.type != ixgbe_mac_82598EB) {
1332 if (!ixgbe_sfp_cage_full(hw)) {
1333 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1338 switch (hw->mac.ops.get_media_type(hw)) {
1340 status = ixgbe_identify_sfp_module_generic(hw);
1344 status = ixgbe_identify_qsfp_module_generic(hw);
1348 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1358 * @hw: pointer to hardware structure
1362 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1366 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1377 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1378 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1384 hw->mac.ops.set_lan_id(hw);
1386 status = hw->phy.ops.read_i2c_eeprom(hw,
1394 if (hw->phy.type != ixgbe_phy_nl)
1395 hw->phy.type = ixgbe_phy_sfp_unsupported;
1398 status = hw->phy.ops.read_i2c_eeprom(hw,
1405 status = hw->phy.ops.read_i2c_eeprom(hw,
1411 status = hw->phy.ops.read_i2c_eeprom(hw,
1434 if (hw->mac.type == ixgbe_mac_82598EB) {
1436 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1438 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1440 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1442 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1445 if (hw->bus.lan_id == 0)
1446 hw->phy.sfp_type =
1449 hw->phy.sfp_type =
1452 hw->phy.ops.read_i2c_eeprom(
1453 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1457 if (hw->bus.lan_id == 0)
1458 hw->phy.sfp_type =
1461 hw->phy.sfp_type =
1464 hw->phy.sfp_type =
1470 if (hw->bus.lan_id == 0)
1471 hw->phy.sfp_type =
1474 hw->phy.sfp_type =
1477 if (hw->bus.lan_id == 0)
1478 hw->phy.sfp_type =
1481 hw->phy.sfp_type =
1484 if (hw->bus.lan_id == 0)
1485 hw->phy.sfp_type =
1488 hw->phy.sfp_type =
1491 if (hw->bus.lan_id == 0)
1492 hw->phy.sfp_type =
1495 hw->phy.sfp_type =
1498 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1502 if (hw->phy.sfp_type != stored_sfp_type)
1503 hw->phy.sfp_setup_needed = TRUE;
1506 hw->phy.multispeed_fiber = FALSE;
1511 hw->phy.multispeed_fiber = TRUE;
1514 if (hw->phy.type != ixgbe_phy_nl) {
1515 hw->phy.id = identifier;
1516 status = hw->phy.ops.read_i2c_eeprom(hw,
1523 status = hw->phy.ops.read_i2c_eeprom(hw,
1530 status = hw->phy.ops.read_i2c_eeprom(hw,
1545 hw->phy.type =
1550 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1552 hw->phy.type = ixgbe_phy_sfp_ftl;
1555 hw->phy.type = ixgbe_phy_sfp_avago;
1558 hw->phy.type = ixgbe_phy_sfp_intel;
1561 hw->phy.type = ixgbe_phy_sfp_unknown;
1572 if (hw->phy.type == ixgbe_phy_nl)
1576 hw->phy.type = ixgbe_phy_sfp_passive_unknown;
1578 hw->phy.type = ixgbe_phy_sfp_active_unknown;
1584 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1585 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1586 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1587 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1588 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1589 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1590 if (hw->phy.type != ixgbe_phy_nl)
1591 hw->phy.type = ixgbe_phy_sfp_unsupported;
1597 if (hw->mac.type == ixgbe_mac_82598EB) {
1602 ixgbe_get_device_caps(hw, &enforce_sfp);
1604 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1605 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1606 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1607 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1608 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1609 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1611 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1614 if (hw->allow_unsupported_sfp == TRUE) {
1615 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1619 if (hw->phy.type != ixgbe_phy_nl)
1620 hw->phy.type =
1632 hw->need_unsupported_sfp_recovery = true;
1636 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1637 if (hw->phy.type != ixgbe_phy_nl) {
1638 hw->phy.id = 0;
1639 hw->phy.type = ixgbe_phy_unknown;
1646 * @hw: pointer to hardware structure
1650 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1658 hw->phy.ops.identify_sfp(hw);
1659 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1662 switch (hw->phy.type) {
1677 hw->phy.ops.read_i2c_eeprom(hw,
1679 hw->phy.ops.read_i2c_eeprom(hw,
1692 hw->phy.ops.read_i2c_eeprom(hw,
1708 * @hw: pointer to hardware structure
1712 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1716 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1729 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1730 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1736 hw->mac.ops.set_lan_id(hw);
1738 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1745 hw->phy.type = ixgbe_phy_sfp_unsupported;
1750 hw->phy.id = identifier;
1752 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1758 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1765 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1766 if (hw->bus.lan_id == 0)
1767 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1769 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1772 if (hw->bus.lan_id == 0)
1773 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1775 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1783 hw->phy.ops.read_i2c_eeprom(hw,
1787 hw->phy.ops.read_i2c_eeprom(hw,
1791 hw->phy.ops.read_i2c_eeprom(hw,
1804 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1805 if (hw->bus.lan_id == 0)
1806 hw->phy.sfp_type =
1809 hw->phy.sfp_type =
1813 hw->phy.type = ixgbe_phy_sfp_unsupported;
1819 if (hw->phy.sfp_type != stored_sfp_type)
1820 hw->phy.sfp_setup_needed = TRUE;
1823 hw->phy.multispeed_fiber = FALSE;
1828 hw->phy.multispeed_fiber = TRUE;
1833 status = hw->phy.ops.read_i2c_eeprom(hw,
1840 status = hw->phy.ops.read_i2c_eeprom(hw,
1847 status = hw->phy.ops.read_i2c_eeprom(hw,
1860 hw->phy.type = ixgbe_phy_qsfp_intel;
1862 hw->phy.type = ixgbe_phy_qsfp_unknown;
1864 ixgbe_get_device_caps(hw, &enforce_sfp);
1867 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1870 if (hw->allow_unsupported_sfp == TRUE) {
1871 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1875 hw->phy.type =
1886 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1887 hw->need_unsupported_sfp_recovery = true;
1891 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1892 hw->phy.id = 0;
1893 hw->phy.type = ixgbe_phy_unknown;
1900 * @hw: pointer to hardware structure
1907 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1912 u16 sfp_type = hw->phy.sfp_type;
1916 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1919 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1922 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1923 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1942 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1959 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1965 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1975 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1995 * @hw: pointer to hardware structure
2001 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
2006 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
2013 * @hw: pointer to hardware structure
2019 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
2022 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
2029 * @hw: pointer to hardware structure
2035 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
2040 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
2047 * @hw: pointer to hardware structure
2051 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
2055 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2062 * @hw: pointer to hardware structure
2071 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2077 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2083 if (hw->mac.type >= ixgbe_mac_X550)
2085 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2089 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2092 ixgbe_i2c_start(hw);
2095 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2099 status = ixgbe_get_i2c_ack(hw);
2103 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2107 status = ixgbe_get_i2c_ack(hw);
2111 ixgbe_i2c_start(hw);
2114 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2118 status = ixgbe_get_i2c_ack(hw);
2122 ixgbe_clock_in_i2c_byte(hw, data);
2124 status = ixgbe_clock_out_i2c_bit(hw, nack);
2128 ixgbe_i2c_stop(hw);
2130 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2134 ixgbe_i2c_bus_clear(hw);
2136 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2152 * @hw: pointer to hardware structure
2160 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2163 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2169 * @hw: pointer to hardware structure
2177 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2180 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2186 * @hw: pointer to hardware structure
2195 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2201 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2205 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2210 ixgbe_i2c_start(hw);
2212 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2216 status = ixgbe_get_i2c_ack(hw);
2220 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2224 status = ixgbe_get_i2c_ack(hw);
2228 status = ixgbe_clock_out_i2c_byte(hw, data);
2232 status = ixgbe_get_i2c_ack(hw);
2236 ixgbe_i2c_stop(hw);
2238 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2242 ixgbe_i2c_bus_clear(hw);
2251 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2258 * @hw: pointer to hardware structure
2266 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2269 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2275 * @hw: pointer to hardware structure
2283 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2286 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2292 * @hw: pointer to hardware structure
2297 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2299 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2303 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2306 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2307 ixgbe_raise_i2c_clk(hw, &i2cctl);
2312 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2317 ixgbe_lower_i2c_clk(hw, &i2cctl);
2326 * @hw: pointer to hardware structure
2332 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2334 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2335 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2336 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2337 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2342 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2343 ixgbe_raise_i2c_clk(hw, &i2cctl);
2348 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2356 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2357 IXGBE_WRITE_FLUSH(hw);
2363 * @hw: pointer to hardware structure
2368 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2377 ixgbe_clock_in_i2c_bit(hw, &bit);
2384 * @hw: pointer to hardware structure
2389 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2400 status = ixgbe_clock_out_i2c_bit(hw, bit);
2407 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2408 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2409 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2410 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2411 IXGBE_WRITE_FLUSH(hw);
2418 * @hw: pointer to hardware structure
2422 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2424 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2427 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2434 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2436 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2437 IXGBE_WRITE_FLUSH(hw);
2439 ixgbe_raise_i2c_clk(hw, &i2cctl);
2447 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2448 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2460 ixgbe_lower_i2c_clk(hw, &i2cctl);
2470 * @hw: pointer to hardware structure
2475 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2477 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2478 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2483 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2485 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2486 IXGBE_WRITE_FLUSH(hw);
2488 ixgbe_raise_i2c_clk(hw, &i2cctl);
2493 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2494 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2496 ixgbe_lower_i2c_clk(hw, &i2cctl);
2504 * @hw: pointer to hardware structure
2509 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2512 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2516 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2518 ixgbe_raise_i2c_clk(hw, &i2cctl);
2523 ixgbe_lower_i2c_clk(hw, &i2cctl);
2540 * @hw: pointer to hardware structure
2546 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2548 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2557 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2561 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2563 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2564 IXGBE_WRITE_FLUSH(hw);
2568 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2569 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2576 * @hw: pointer to hardware structure
2582 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2586 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2587 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2589 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2590 IXGBE_WRITE_FLUSH(hw);
2598 * @hw: pointer to hardware structure
2605 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2607 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2613 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2615 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2618 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2619 IXGBE_WRITE_FLUSH(hw);
2628 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2629 IXGBE_WRITE_FLUSH(hw);
2633 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2634 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2646 * @hw: pointer to hardware structure
2652 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2654 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2661 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2662 IXGBE_WRITE_FLUSH(hw);
2666 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2676 * @hw: pointer to hardware structure
2681 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2688 ixgbe_i2c_start(hw);
2689 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2691 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2694 ixgbe_raise_i2c_clk(hw, &i2cctl);
2699 ixgbe_lower_i2c_clk(hw, &i2cctl);
2705 ixgbe_i2c_start(hw);
2708 ixgbe_i2c_stop(hw);
2713 * @hw: pointer to hardware structure
2717 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2724 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2728 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2742 * @hw: pointer to hardware structure
2745 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2750 if (!on && ixgbe_mng_present(hw))
2753 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2762 if (ixgbe_check_reset_blocked(hw))
2767 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
Indexes created Thu Oct 16 14:10:15 GMT 2025