Lines Matching refs:phy
120 u32 swfw_mask = hw->phy.phy_semaphore_mask;
197 u32 swfw_mask = hw->phy.phy_semaphore_mask;
250 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
257 struct ixgbe_phy_info *phy = &hw->phy;
261 /* PHY */
262 phy->ops.identify = ixgbe_identify_phy_generic;
263 phy->ops.reset = ixgbe_reset_phy_generic;
264 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
265 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
266 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
267 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
268 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
269 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
270 phy->ops.check_link = NULL;
271 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
272 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
273 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
274 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
275 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
276 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
277 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
278 phy->ops.identify_sfp = ixgbe_identify_module_generic;
279 phy->sfp_type = ixgbe_sfp_type_unknown;
280 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
281 phy->ops.write_i2c_byte_unlocked =
283 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
288 * ixgbe_probe_phy - Probe a single address for a PHY
290 * @phy_addr: PHY address to probe
292 * Returns TRUE if PHY found
299 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
307 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
309 if (hw->phy.type == ixgbe_phy_unknown) {
310 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
315 hw->phy.type = ixgbe_phy_cu_unknown;
317 hw->phy.type = ixgbe_phy_generic;
336 if (!hw->phy.phy_semaphore_mask) {
338 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
340 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
343 if (hw->phy.type != ixgbe_phy_unknown)
346 if (hw->phy.nw_mng_if_sel) {
347 phy_addr = (hw->phy.nw_mng_if_sel &
363 /* Certain media types do not have a phy so an address will not
368 hw->phy.addr = 0;
403 * ixgbe_validate_phy_addr - Determines phy address is valid
405 * @phy_addr: PHY address
415 hw->phy.addr = phy_addr;
416 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
422 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
428 * ixgbe_get_phy_id - Get the phy type
440 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
445 hw->phy.id = (u32)(phy_id_high << 16);
446 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
449 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
450 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
459 * ixgbe_get_phy_type_from_id - Get the phy type
460 * @phy_id: PHY ID information
499 * ixgbe_reset_phy_generic - Performs a PHY reset
510 if (hw->phy.type == ixgbe_phy_unknown)
513 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
516 /* Don't reset PHY if it's shut down due to overtemp. */
517 if (!hw->phy.reset_if_overtemp &&
518 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
526 * Perform soft PHY reset to the PHY_XS.
527 * This will cause a soft reset to the PHY
529 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
540 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
541 status = hw->phy.ops.read_reg(hw,
553 status = hw->phy.ops.read_reg(hw,
570 "PHY reset polling failed to complete.\n");
578 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
581 * @reg_addr: 32 bit address of PHY register to read
583 * @phy_data: Pointer to read data from PHY register
593 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
613 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
614 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
624 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
643 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
644 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
660 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
663 * @reg_addr: 32 bit address of PHY register to read
665 * @phy_data: Pointer to read data from PHY register
671 u32 gssr = hw->phy.phy_semaphore_mask;
678 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
686 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
689 * @reg_addr: 32 bit PHY register to write
691 * @phy_data: Data to write to the PHY register
704 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
723 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
733 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
752 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
760 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
763 * @reg_addr: 32 bit PHY register to write
765 * @phy_data: Data to write to the PHY register
771 u32 gssr = hw->phy.phy_semaphore_mask;
776 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
790 * Restart auto-negotiation and PHY and waits for completion.
804 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
809 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
813 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
817 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
824 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
830 if ((hw->phy.autoneg_advertised &
838 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
842 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
847 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
853 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
857 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
861 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_100_FULL) {
865 hw->phy.ops.read_reg(hw, MDIO_PMAPMD_CTRL1, MDIO_MMD_PMAPMD,
869 hw->phy.ops.write_reg(hw, MDIO_PMAPMD_CTRL1,MDIO_MMD_PMAPMD,
873 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
878 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
881 /* Blocked by MNG FW so don't reset PHY */
885 /* Restart PHY auto-negotiation. */
886 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
891 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
916 hw->phy.autoneg_advertised = 0;
919 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
922 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
925 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
928 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
931 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
934 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
943 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
946 * Determines the supported link capabilities by reading the PHY auto
954 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
961 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
963 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
965 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
969 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
970 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
974 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
998 if (!hw->phy.speeds_supported)
1001 *speed = hw->phy.speeds_supported;
1012 * the PHY.
1031 * Check current speed and link status of the PHY register.
1037 status = hw->phy.ops.read_reg(hw,
1060 * Restart auto-negotiation and PHY and waits for completion.
1075 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1080 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1083 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1090 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1095 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1098 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1105 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1110 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1113 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1118 /* Blocked by MNG FW so don't reset PHY */
1122 /* Restart PHY auto-negotiation. */
1123 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1128 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1135 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1137 * @firmware_version: pointer to the PHY Firmware Version
1146 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1154 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1156 * @firmware_version: pointer to the PHY Firmware Version
1165 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1173 * ixgbe_reset_phy_nl - Performs a PHY reset
1191 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1194 /* reset the PHY and poll for completion */
1195 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1200 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1208 DEBUGOUT("PHY reset did not complete.\n");
1223 * Read control word from PHY init contents offset
1250 hw->phy.ops.write_reg(hw, phy_offset,
1333 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1348 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1360 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1366 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1378 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1386 status = hw->phy.ops.read_i2c_eeprom(hw,
1394 if (hw->phy.type != ixgbe_phy_nl)
1395 hw->phy.type = ixgbe_phy_sfp_unsupported;
1398 status = hw->phy.ops.read_i2c_eeprom(hw,
1405 status = hw->phy.ops.read_i2c_eeprom(hw,
1411 status = hw->phy.ops.read_i2c_eeprom(hw,
1436 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1438 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1440 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1442 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1446 hw->phy.sfp_type =
1449 hw->phy.sfp_type =
1452 hw->phy.ops.read_i2c_eeprom(
1458 hw->phy.sfp_type =
1461 hw->phy.sfp_type =
1464 hw->phy.sfp_type =
1471 hw->phy.sfp_type =
1474 hw->phy.sfp_type =
1478 hw->phy.sfp_type =
1481 hw->phy.sfp_type =
1485 hw->phy.sfp_type =
1488 hw->phy.sfp_type =
1492 hw->phy.sfp_type =
1495 hw->phy.sfp_type =
1498 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1502 if (hw->phy.sfp_type != stored_sfp_type)
1503 hw->phy.sfp_setup_needed = TRUE;
1505 /* Determine if the SFP+ PHY is dual speed or not. */
1506 hw->phy.multispeed_fiber = FALSE;
1511 hw->phy.multispeed_fiber = TRUE;
1513 /* Determine PHY vendor */
1514 if (hw->phy.type != ixgbe_phy_nl) {
1515 hw->phy.id = identifier;
1516 status = hw->phy.ops.read_i2c_eeprom(hw,
1523 status = hw->phy.ops.read_i2c_eeprom(hw,
1530 status = hw->phy.ops.read_i2c_eeprom(hw,
1545 hw->phy.type =
1550 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1552 hw->phy.type = ixgbe_phy_sfp_ftl;
1555 hw->phy.type = ixgbe_phy_sfp_avago;
1558 hw->phy.type = ixgbe_phy_sfp_intel;
1561 hw->phy.type = ixgbe_phy_sfp_unknown;
1571 /* Keep phy.type for ixgbe_phy_nl */
1572 if (hw->phy.type == ixgbe_phy_nl)
1576 hw->phy.type = ixgbe_phy_sfp_passive_unknown;
1578 hw->phy.type = ixgbe_phy_sfp_active_unknown;
1584 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1585 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1586 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1587 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1588 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1589 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1590 if (hw->phy.type != ixgbe_phy_nl)
1591 hw->phy.type = ixgbe_phy_sfp_unsupported;
1604 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1605 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1606 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1607 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1608 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1609 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1610 /* Make sure we're a supported PHY type */
1611 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1619 if (hw->phy.type != ixgbe_phy_nl)
1620 hw->phy.type =
1636 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1637 if (hw->phy.type != ixgbe_phy_nl) {
1638 hw->phy.id = 0;
1639 hw->phy.type = ixgbe_phy_unknown;
1658 hw->phy.ops.identify_sfp(hw);
1659 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1662 switch (hw->phy.type) {
1677 hw->phy.ops.read_i2c_eeprom(hw,
1679 hw->phy.ops.read_i2c_eeprom(hw,
1692 hw->phy.ops.read_i2c_eeprom(hw,
1710 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1716 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1730 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1738 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1745 hw->phy.type = ixgbe_phy_sfp_unsupported;
1750 hw->phy.id = identifier;
1752 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1758 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1765 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1767 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1769 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1773 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1775 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1783 hw->phy.ops.read_i2c_eeprom(hw,
1787 hw->phy.ops.read_i2c_eeprom(hw,
1791 hw->phy.ops.read_i2c_eeprom(hw,
1804 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1806 hw->phy.sfp_type =
1809 hw->phy.sfp_type =
1813 hw->phy.type = ixgbe_phy_sfp_unsupported;
1819 if (hw->phy.sfp_type != stored_sfp_type)
1820 hw->phy.sfp_setup_needed = TRUE;
1822 /* Determine if the QSFP+ PHY is dual speed or not. */
1823 hw->phy.multispeed_fiber = FALSE;
1828 hw->phy.multispeed_fiber = TRUE;
1830 /* Determine PHY vendor for optical modules */
1833 status = hw->phy.ops.read_i2c_eeprom(hw,
1840 status = hw->phy.ops.read_i2c_eeprom(hw,
1847 status = hw->phy.ops.read_i2c_eeprom(hw,
1860 hw->phy.type = ixgbe_phy_qsfp_intel;
1862 hw->phy.type = ixgbe_phy_qsfp_unknown;
1866 /* Make sure we're a supported PHY type */
1867 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1875 hw->phy.type =
1886 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1891 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1892 hw->phy.id = 0;
1893 hw->phy.type = ixgbe_phy_unknown;
1899 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1905 * so it returns the offsets to the phy init sequence block.
1912 u16 sfp_type = hw->phy.sfp_type;
1916 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1919 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1923 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1941 /* Read offset to PHY init contents */
2006 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
2022 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
2040 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
2055 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2077 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2201 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2728 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2741 * ixgbe_set_copper_phy_power - Control power for copper phy
2753 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2767 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
Indexes created Sat Mar 21 00:23:06 UTC 2026