Lines Matching defs:que
714 struct ix_queue *que;
724 for (i = 0, que = sc->queues; i < sc->num_queues; i++, que++)
725 que->disabled_count = 0;
784 for (i = 0, que = sc->queues; i < sc->num_queues; i++, que++)
785 mask |= (1 << que->msix);
833 struct ix_queue *que = &sc->queues[vector];
837 mutex_enter(&que->dc_mtx);
838 if (que->disabled_count > 0 && --que->disabled_count > 0)
844 mutex_exit(&que->dc_mtx);
854 struct ix_queue *que = &sc->queues[vector];
858 mutex_enter(&que->dc_mtx);
859 if (que->disabled_count++ > 0)
865 mutex_exit(&que->dc_mtx);
884 struct ix_queue *que = arg;
885 struct ixgbe_softc *sc = que->sc;
886 struct tx_ring *txr = que->txr;
887 struct rx_ring *rxr = que->rxr;
891 ixv_disable_queue(sc, que->msix);
892 IXGBE_EVC_ADD(&que->irqs, 1);
898 more = ixgbe_rxeof(que);
915 if (que->eitr_setting)
916 ixv_eitr_write(sc, que->msix, que->eitr_setting);
918 que->eitr_setting = 0;
952 que->eitr_setting = newitr;
962 softint_schedule(que->que_si);
964 ixv_enable_queue(sc, que->msix);
1285 struct ix_queue *que = sc->queues;
1304 que = sc->queues;
1305 for (i = 0; i < sc->num_queues; i++, que++) {
1306 struct tx_ring *txr = que->txr;
1331 que = sc->queues;
1332 for (i = 0; i < sc->num_queues; i++, que++) {
1334 if (que->txr->busy)
1335 queues |= ((u64)1 << que->me);
1341 if (que->busy == IXGBE_QUEUE_HUNG) {
1344 sc->active_queues &= ~((u64)1 << que->me);
1348 if ((sc->active_queues & ((u64)1 << que->me)) == 0)
1349 sc->active_queues |= ((u64)1 << que->me);
1351 if (que->busy >= IXGBE_MAX_TX_BUSY) {
1354 que->txr->busy = IXGBE_QUEUE_HUNG;
1556 struct ix_queue *que = sc->queues;
1560 for (i = 0; i < sc->num_queues; i++, que++, txr++) {
1565 if (que->que_si != NULL)
1566 softint_disestablish(que->que_si);
1592 struct ix_queue *que = sc->queues;
1598 for (int i = 0; i < sc->num_queues; i++, que++) {
1599 if (que->res != NULL)
2320 struct ix_queue *que = sc->queues;
2326 for (i = 0; i < sc->num_queues; i++, que++)
2327 mask |= (1 << que->msix);
2332 que = sc->queues;
2333 for (i = 0; i < sc->num_queues; i++, que++)
2334 ixv_enable_queue(sc, que->msix);
2345 struct ix_queue *que = sc->queues;
2352 for (int i = 0; i < sc->num_queues; i++, que++)
2353 ixv_disable_queue(sc, que->msix);
2394 struct ix_queue *que = sc->queues;
2398 for (int i = 0; i < sc->num_queues; i++, que++) {
2400 ixv_set_ivar(sc, i, que->msix, 0);
2402 ixv_set_ivar(sc, i, que->msix, 1);
2404 ixv_eitr_write(sc, que->msix, IXGBE_EITR_DEFAULT);
2484 struct ix_queue *que = (struct ix_queue *)node.sysctl_data;
2485 struct ixgbe_softc *sc = que->sc;
2489 if (que == NULL)
2491 reg = IXGBE_READ_REG(&que->sc->hw, IXGBE_VTEITR(que->msix));
2521 ixv_eitr_write(sc, que->msix, reg);
3301 struct ix_queue *que = context;
3302 struct ixgbe_softc *sc = que->sc;
3303 struct tx_ring *txr = que->txr;
3307 IXGBE_EVC_ADD(&que->handleq, 1);
3317 if ((&sc->queues[0] == que)
3321 more |= ixgbe_rxeof(que);
3323 IXGBE_EVC_ADD(&que->req, 1);
3330 &que->wq_cookie, curcpu());
3332 softint_schedule(que->que_si);
3338 ixv_enable_queue(sc, que->msix);
3349 struct ix_queue *que = container_of(wk, struct ix_queue, wq_cookie);
3355 ixv_handle_que(que);
3365 struct ix_queue *que = sc->queues;
3389 for (int i = 0; i < sc->num_queues; i++, vector++, que++, txr++) {
3398 que->res = sc->osdep.ihs[i] = pci_intr_establish_xname(pc,
3399 sc->osdep.intrs[i], IPL_NET, ixv_msix_que, que,
3401 if (que->res == NULL) {
3405 "Failed to register QUE handler\n");
3409 que->msix = vector;
3410 sc->active_queues |= (u64)(1 << que->msix);
3430 que->que_si
3432 ixv_handle_que, que);
3433 if (que->que_si == NULL) {
Indexes created Wed Oct 01 15:09:59 GMT 2025