Lines Matching defs:mlx
61 * PCI front-end for the mlx(4) driver.
204 struct mlx_softc *mlx;
215 mlx = device_private(self);
220 mlx->mlx_dv = self;
221 mlx->mlx_dmat = pa->pa_dmat;
222 mlx->mlx_ci.ci_iftype = mpi->mpi_iftype;
254 mlx->mlx_iot = memt;
255 mlx->mlx_ioh = memh;
257 mlx->mlx_iot = iot;
258 mlx->mlx_ioh = ioh;
275 mlx->mlx_ih = pci_intr_establish_xname(pc, ih, IPL_BIO, mlx_intr, mlx,
277 if (mlx->mlx_ih == NULL) {
286 switch (mlx->mlx_ci.ci_iftype) {
289 mlx->mlx_submit = mlx_v3_submit;
290 mlx->mlx_findcomplete = mlx_v3_findcomplete;
291 mlx->mlx_intaction = mlx_v3_intaction;
292 mlx->mlx_fw_handshake = mlx_v3_fw_handshake;
294 mlx->mlx_reset = mlx_v3_reset;
299 mlx->mlx_submit = mlx_v4_submit;
300 mlx->mlx_findcomplete = mlx_v4_findcomplete;
301 mlx->mlx_intaction = mlx_v4_intaction;
302 mlx->mlx_fw_handshake = mlx_v4_fw_handshake;
306 mlx->mlx_submit = mlx_v5_submit;
307 mlx->mlx_findcomplete = mlx_v5_findcomplete;
308 mlx->mlx_intaction = mlx_v5_intaction;
309 mlx->mlx_fw_handshake = mlx_v5_fw_handshake;
313 mlx_init(mlx, intrstr);
327 mlx_v3_submit(struct mlx_softc *mlx, struct mlx_ccb *mc)
331 if ((mlx_inb(mlx, MLX_V3REG_IDB) & MLX_V3_IDB_FULL) == 0) {
333 bus_space_write_region_1(mlx->mlx_iot, mlx->mlx_ioh,
335 bus_space_barrier(mlx->mlx_iot, mlx->mlx_ioh,
340 mlx_outb(mlx, MLX_V3REG_IDB, MLX_V3_IDB_FULL);
354 mlx_v3_findcomplete(struct mlx_softc *mlx, u_int *slot, u_int *status)
358 if ((mlx_inb(mlx, MLX_V3REG_ODB) & MLX_V3_ODB_SAVAIL) != 0) {
359 *slot = mlx_inb(mlx, MLX_V3REG_STATUS_IDENT);
360 *status = mlx_inw(mlx, MLX_V3REG_STATUS);
363 mlx_outb(mlx, MLX_V3REG_ODB, MLX_V3_ODB_SAVAIL);
364 mlx_outb(mlx, MLX_V3REG_IDB, MLX_V3_IDB_SACK);
377 mlx_v3_intaction(struct mlx_softc *mlx, int action)
380 mlx_outb(mlx, MLX_V3REG_IE, action != 0);
390 mlx_v3_fw_handshake(struct mlx_softc *mlx, int *error, int *param1, int *param2)
395 if ((mlx->mlx_flags & MLXF_FW_INITTED) == 0) {
396 mlx_outb(mlx, MLX_V3REG_IDB, MLX_V3_IDB_SACK);
398 mlx->mlx_flags |= MLXF_FW_INITTED;
402 if ((mlx_inb(mlx, MLX_V3REG_IDB) & MLX_V3_IDB_INIT_BUSY) == 0)
406 fwerror = mlx_inb(mlx, MLX_V3REG_FWERROR);
413 *param1 = mlx_inb(mlx, MLX_V3REG_FWERROR_PARAM1);
414 *param2 = mlx_inb(mlx, MLX_V3REG_FWERROR_PARAM2);
417 mlx_outb(mlx, MLX_V3REG_FWERROR, 0);
427 mlx_v3_reset(struct mlx_softc *mlx)
431 mlx_outb(mlx, MLX_V3REG_IDB, MLX_V3_IDB_SACK);
437 if ((mlx_inb(mlx, MLX_V3REG_IDB) & MLX_V3_IDB_SACK) == 0)
446 mlx_outb(mlx, MLX_V3REG_IDB, MLX_V3_IDB_RESET);
451 if ((mlx_inb(mlx, MLX_V3REG_IDB) & MLX_V3_IDB_RESET) == 0)
475 mlx_v4_submit(struct mlx_softc *mlx, struct mlx_ccb *mc)
479 if ((mlx_inl(mlx, MLX_V4REG_IDB) & MLX_V4_IDB_FULL) == 0) {
481 bus_space_write_region_1(mlx->mlx_iot, mlx->mlx_ioh,
483 bus_space_barrier(mlx->mlx_iot, mlx->mlx_ioh,
488 mlx_outl(mlx, MLX_V4REG_IDB, MLX_V4_IDB_HWMBOX_CMD);
502 mlx_v4_findcomplete(struct mlx_softc *mlx, u_int *slot, u_int *status)
506 if ((mlx_inl(mlx, MLX_V4REG_ODB) & MLX_V4_ODB_HWSAVAIL) != 0) {
507 *slot = mlx_inb(mlx, MLX_V4REG_STATUS_IDENT);
508 *status = mlx_inw(mlx, MLX_V4REG_STATUS);
511 mlx_outl(mlx, MLX_V4REG_ODB, MLX_V4_ODB_HWMBOX_ACK);
512 mlx_outl(mlx, MLX_V4REG_IDB, MLX_V4_IDB_SACK);
525 mlx_v4_intaction(struct mlx_softc *mlx, int action)
534 mlx_outl(mlx, MLX_V4REG_IE, ier);
544 mlx_v4_fw_handshake(struct mlx_softc *mlx, int *error, int *param1, int *param2)
549 if ((mlx->mlx_flags & MLXF_FW_INITTED) == 0) {
550 mlx_outl(mlx, MLX_V4REG_IDB, MLX_V4_IDB_SACK);
552 mlx->mlx_flags |= MLXF_FW_INITTED;
556 if ((mlx_inl(mlx, MLX_V4REG_IDB) & MLX_V4_IDB_INIT_BUSY) == 0)
560 fwerror = mlx_inb(mlx, MLX_V4REG_FWERROR);
566 *param1 = mlx_inb(mlx, MLX_V4REG_FWERROR_PARAM1);
567 *param2 = mlx_inb(mlx, MLX_V4REG_FWERROR_PARAM2);
570 mlx_outb(mlx, MLX_V4REG_FWERROR, 0);
586 mlx_v5_submit(struct mlx_softc *mlx, struct mlx_ccb *mc)
590 if ((mlx_inb(mlx, MLX_V5REG_IDB) & MLX_V5_IDB_EMPTY) != 0) {
592 bus_space_write_region_1(mlx->mlx_iot, mlx->mlx_ioh,
594 bus_space_barrier(mlx->mlx_iot, mlx->mlx_ioh,
599 mlx_outb(mlx, MLX_V5REG_IDB, MLX_V5_IDB_HWMBOX_CMD);
613 mlx_v5_findcomplete(struct mlx_softc *mlx, u_int *slot, u_int *status)
617 if ((mlx_inb(mlx, MLX_V5REG_ODB) & MLX_V5_ODB_HWSAVAIL) != 0) {
618 *slot = mlx_inb(mlx, MLX_V5REG_STATUS_IDENT);
619 *status = mlx_inw(mlx, MLX_V5REG_STATUS);
622 mlx_outb(mlx, MLX_V5REG_ODB, MLX_V5_ODB_HWMBOX_ACK);
623 mlx_outb(mlx, MLX_V5REG_IDB, MLX_V5_IDB_SACK);
636 mlx_v5_intaction(struct mlx_softc *mlx, int action)
645 mlx_outb(mlx, MLX_V5REG_IE, ier);
655 mlx_v5_fw_handshake(struct mlx_softc *mlx, int *error, int *param1, int *param2)
660 if ((mlx->mlx_flags & MLXF_FW_INITTED) == 0) {
661 mlx_outb(mlx, MLX_V5REG_IDB, MLX_V5_IDB_SACK);
663 mlx->mlx_flags |= MLXF_FW_INITTED;
667 if ((mlx_inb(mlx, MLX_V5REG_IDB) & MLX_V5_IDB_INIT_DONE) != 0)
671 fwerror = mlx_inb(mlx, MLX_V5REG_FWERROR);
677 *param1 = mlx_inb(mlx, MLX_V5REG_FWERROR_PARAM1);
678 *param2 = mlx_inb(mlx, MLX_V5REG_FWERROR_PARAM2);
681 mlx_outb(mlx, MLX_V5REG_FWERROR, 0xff);
686 MODULE(MODULE_CLASS_DRIVER, mlx_pci, "mlx,pci");
Indexes created Sun Sep 21 19:09:51 GMT 2025