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Lines Matching refs:mlx_inb

331 	if ((mlx_inb(mlx, MLX_V3REG_IDB) & MLX_V3_IDB_FULL) == 0) {
358 	if ((mlx_inb(mlx, MLX_V3REG_ODB) & MLX_V3_ODB_SAVAIL) != 0) {
359 		*slot = mlx_inb(mlx, MLX_V3REG_STATUS_IDENT);
402 	if ((mlx_inb(mlx, MLX_V3REG_IDB) & MLX_V3_IDB_INIT_BUSY) == 0)
406 	fwerror = mlx_inb(mlx, MLX_V3REG_FWERROR);
413 	*param1 = mlx_inb(mlx, MLX_V3REG_FWERROR_PARAM1);
414 	*param2 = mlx_inb(mlx, MLX_V3REG_FWERROR_PARAM2);
437 		if ((mlx_inb(mlx, MLX_V3REG_IDB) & MLX_V3_IDB_SACK) == 0)
451 		if ((mlx_inb(mlx, MLX_V3REG_IDB) & MLX_V3_IDB_RESET) == 0)
507 		*slot = mlx_inb(mlx, MLX_V4REG_STATUS_IDENT);
560 	fwerror = mlx_inb(mlx, MLX_V4REG_FWERROR);
566 	*param1 = mlx_inb(mlx, MLX_V4REG_FWERROR_PARAM1);
567 	*param2 = mlx_inb(mlx, MLX_V4REG_FWERROR_PARAM2);
590 	if ((mlx_inb(mlx, MLX_V5REG_IDB) & MLX_V5_IDB_EMPTY) != 0) {
617 	if ((mlx_inb(mlx, MLX_V5REG_ODB) & MLX_V5_ODB_HWSAVAIL) != 0) {
618 		*slot = mlx_inb(mlx, MLX_V5REG_STATUS_IDENT);
667 	if ((mlx_inb(mlx, MLX_V5REG_IDB) & MLX_V5_IDB_INIT_DONE) != 0)
671 	fwerror = mlx_inb(mlx, MLX_V5REG_FWERROR);
677 	*param1 = mlx_inb(mlx, MLX_V5REG_FWERROR_PARAM1);
678 	*param2 = mlx_inb(mlx, MLX_V5REG_FWERROR_PARAM2);