Lines Matching refs:sc_regh
75 bus_space_handle_t sc_regh;
151 reg = (bus_space_read_4(sc->sc_memt, sc->sc_regh,
161 reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, R128_PC_NGUI_CTLSTAT);
163 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_PC_NGUI_CTLSTAT, reg);
165 reg = bus_space_read_4(sc->sc_memt, sc->sc_regh,
247 &tag, &sc->sc_regh, &sc->sc_reg, &sc->sc_regsize)) {
337 reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, R128_LVDS_GEN_CNTL);
652 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_PALETTE_INDEX, idx);
653 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_PALETTE_DATA, reg);
665 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_CRTC_OFFSET, 0);
666 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_DEFAULT_OFFSET, 0);
668 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_DEFAULT_PITCH,
670 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_AUX_SC_CNTL, 0);
671 bus_space_write_4(sc->sc_memt, sc->sc_regh,
674 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_SC_TOP_LEFT, 0);
675 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_SC_BOTTOM_RIGHT,
677 bus_space_write_4(sc->sc_memt, sc->sc_regh,
683 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_DP_DATATYPE,
686 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_DP_DATATYPE, 0);
690 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_SRC_PITCH,
692 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_DST_PITCH,
694 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_SRC_OFFSET, 0);
695 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_DST_OFFSET, 0);
696 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_DP_WRITE_MASK,
727 reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, R128_CRTC_GEN_CNTL);
731 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_CRTC_GEN_CNTL, reg);
732 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_CRTC_PITCH, sc->sc_width >> 3);
742 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_DP_GUI_MASTER_CNTL,
748 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_DP_BRUSH_FRGD_CLR,
750 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_DP_CNTL,
753 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_DST_X_Y,
755 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_DST_WIDTH_HEIGHT,
767 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_DP_GUI_MASTER_CNTL,
786 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_DP_CNTL, dp_cntl);
789 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_SRC_X_Y,
791 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_DST_X_Y,
793 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_DST_WIDTH_HEIGHT,
865 bus_space_write_4(sc->sc_memt, sc->sc_regh,
874 bus_space_write_4(sc->sc_memt, sc->sc_regh,
879 bus_space_write_4(sc->sc_memt, sc->sc_regh,
881 bus_space_write_4(sc->sc_memt, sc->sc_regh,
890 bus_space_write_4(sc->sc_memt, sc->sc_regh,
892 bus_space_write_4(sc->sc_memt, sc->sc_regh,
896 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_SRC_X_Y, 0);
899 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_DST_X_Y,
901 bus_space_write_4(sc->sc_memt, sc->sc_regh,
912 sc->sc_regh, R128_HOST_DATA0, reg);
923 sc->sc_regh, R128_HOST_DATA0, reg);
968 bus_space_write_4(sc->sc_memt, sc->sc_regh,
976 bus_space_write_4(sc->sc_memt, sc->sc_regh,
982 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_SRC_X_Y, 0);
983 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_DST_X_Y,
985 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_DST_WIDTH_HEIGHT,
1023 bus_space_write_stream_4(sc->sc_memt, sc->sc_regh,
1041 bus_space_write_stream_4(sc->sc_memt, sc->sc_regh,
1143 reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, R128_LVDS_GEN_CNTL);
1146 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_LVDS_GEN_CNTL, reg);
1159 reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, R128_LVDS_GEN_CNTL);
1163 bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_LVDS_GEN_CNTL, reg);
Indexes created Mon Oct 20 20:10:13 GMT 2025