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Lines Matching refs:CLR32

782 		CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2);
1039 		CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS);
1043 		CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS);
2304 			CLR32(sc, AVIVO_D1GRPH_CONTROL, AVIVO_D1GRPH_MACRO_ADDRESS_MODE);
2309 			CLR32(sc, AVIVO_D2GRPH_CONTROL, AVIVO_D1GRPH_MACRO_ADDRESS_MODE);
2534 		CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN);
2536 		CLR32(sc, RADEON_CRTC_EXT_CNTL,
2539 		CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B);
2549 		CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN);
2550 		CLR32(sc, RADEON_CRTC2_GEN_CNTL,
2603 			CLR32(sc, AVIVO_D1CRTC_CONTROL, AVIVO_CRTC_EN);
2604 			CLR32(sc, AVIVO_D2CRTC_CONTROL, AVIVO_CRTC_EN);
2628 			CLR32(sc, fpreg, fpval);
2630 			CLR32(sc, reg, mask);
2912 				CLR32(sc, RADEON_DAC_CNTL2,
4187 			CLR32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK);
4220 			CLR32(dp->rd_softc, gencntl, bit);
4222 			CLR32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK);