Cross Reference: /src/sys/dev/pci/radeonfb.c

Lines Matching refs:GET32
206 #define	PRINTREG(r)	DPRINTF((#r " = %08x\n", GET32(sc, r)))
587 	sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL);
762 	v = GET32(sc, RADEON_DAC_CNTL);
1622 	saved = GET32(sc, reg);
1624 	if (GET32(sc, reg) != v) {
2351 		if (GET32(sc, AVIVO_D1CRTC_CONTROL) & AVIVO_CRTC_EN) {
2353 			dp->rd_stride = GET32(sc, AVIVO_D1GRPH_PITCH);
2356 		if (GET32(sc, AVIVO_D2CRTC_CONTROL) & AVIVO_CRTC_EN) {
2358 			dp->rd_stride = GET32(sc, AVIVO_D2GRPH_PITCH);
2507 	v = GET32(sc, RADEON_CRTC_EXT_CNTL);
2519 	hd = ((GET32(sc, htotaldisp) >> 16) + 1) * 8;
2520 	vd = (GET32(sc, vtotaldisp) >> 16) + 1;
2646 		reg = GET32(sc, AVIVO_D1CRTC_CONTROL);
2657 	return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0);
2824 	(void)GET32(sc, AVIVO_MC_INDEX);
2825 	data = GET32(sc, AVIVO_MC_DATA);
2827 	(void)GET32(sc, AVIVO_MC_INDEX);
2836 	(void)GET32(sc, AVIVO_MC_INDEX);
2839 	(void)GET32(sc, AVIVO_MC_INDEX);
2852 		gen = GET32(sc, RADEON_CRTC_GEN_CNTL);
2854 		ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS;
2855 		agploc = GET32(sc, RADEON_MC_AGP_LOCATION);
2864 			gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL);
2872 	aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE);
2873 	apersize = GET32(sc, RADEON_CONFIG_APER_SIZE);
2955 	PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS));
3123 	save = GET32(sc, RADEON_CLOCK_CNTL_INDEX);
3126 	tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA);
3769 	while ((GET32(sc, RADEON_RBBM_STATUS) &
3780 		if ((GET32(sc, RADEON_RBBM_STATUS) &
3787 		    XNAME(sc), GET32(sc, RADEON_RBBM_STATUS));
3798 		while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) {
3804 		while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) &
3837 		psel = GET32(sc, R400_GB_PIPE_SELECT);
3888 	(void)GET32(sc, RADEON_DP_DATATYPE);
3923 	clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX);
3934 	hpc = GET32(sc, RADEON_HOST_PATH_CNTL);
3935 	rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET);
3941 		GET32(sc, RADEON_RBBM_SOFT_RESET);
3956 		GET32(sc, RADEON_RBBM_SOFT_RESET);
3964 		GET32(sc, RADEON_RBBM_SOFT_RESET);
3968 	GET32(sc, RADEON_HOST_PATH_CNTL);
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