Lines Matching refs:PUT32
609 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27);
758 PUT32(sc, RADEON_DAC_CNTL, v);
762 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203);
1595 PUT32(sc, reg, v);
1599 PUT32(sc, reg, saved);
2306 PUT32(sc, AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, 0);
2311 PUT32(sc, AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, 0);
2326 PUT32(sc, RADEON_OVR_CLR, 0);
2327 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0);
2328 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0);
2329 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0);
2330 PUT32(sc, RADEON_SUBPIC_CNTL, 0);
2331 PUT32(sc, RADEON_VIPH_CONTROL, 0);
2332 PUT32(sc, RADEON_I2C_CNTL_1, 0);
2333 PUT32(sc, RADEON_GEN_INT_CNTL, 0);
2334 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0);
2335 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0);
2449 PUT32(sc, gencntl, v);
2465 PUT32(sc, RADEON_CRTC_EXT_CNTL, v);
2480 PUT32(sc, htotaldisp, v);
2484 PUT32(sc, fphtotaldisp, v);
2494 PUT32(sc, hsyncstrt, v);
2497 PUT32(sc, fphsyncstrt, v);
2506 PUT32(sc, vtotaldisp, v);
2509 PUT32(sc, fpvtotaldisp, v);
2520 PUT32(sc, vsyncstrt, v);
2523 PUT32(sc, fpvsyncstrt, v);
2531 PUT32(sc, RADEON_CRTC_OFFSET, 0);
2532 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0);
2533 PUT32(sc, RADEON_CRTC_PITCH, pitch);
2546 PUT32(sc, RADEON_CRTC2_OFFSET, 0);
2547 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0);
2548 PUT32(sc, RADEON_CRTC2_PITCH, pitch);
2743 PUT32(sc, AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000);
2746 PUT32(sc, AVIVO_MC_INDEX, 0);
2755 PUT32(sc, AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000);
2757 PUT32(sc, AVIVO_MC_DATA, data);
2758 PUT32(sc, AVIVO_MC_INDEX, 0);
2776 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B);
2777 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS);
2779 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS);
2780 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B);
2785 PUT32(sc, RADEON_CRTC2_GEN_CNTL,
2809 PUT32(sc, RADEON_HOST_PATH_CNTL, 0);
2818 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc);
2819 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc);
2823 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase);
2826 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase);
2828 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase);
2831 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen);
2832 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext);
2835 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2);
2839 PUT32(sc, RADEON_AGP_CNTL, 0x00100000);
2846 PUT32(sc, RADEON_BUS_CNTL,
2858 PUT32(sc, RADEON_BUS_CNTL1, 0xf0);
2859 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */
2860 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND);
2861 PUT32(sc, RADEON_RBBM_CNTL,
2868 PUT32(sc, RADEON_AGP_CNTL, 0x00100000);
2869 PUT32(sc, RADEON_HOST_PATH_CNTL, 0);
2871 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400);
2874 PUT32(sc, RADEON_GEN_INT_CNTL, 0);
2875 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS));
2890 PUT32(sc, AVIVO_DC_LUT_RW_SELECT, 1);
2892 PUT32(sc, AVIVO_DC_LUT_RW_SELECT, 0);
2894 PUT32(sc, AVIVO_DC_LUT_RW_INDEX, idx);
2895 PUT32(sc, AVIVO_DC_LUT_30_COLOR,
2915 PUT32(sc, RADEON_PALETTE_INDEX, idx);
2916 PUT32(sc, RADEON_PALETTE_30_DATA,
3046 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp);
3048 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save);
3098 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
3108 PUT32(sc, RADEON_SC_LEFT, xd);
3109 PUT32(sc, RADEON_SC_RIGHT, xd + w);
3110 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg);
3111 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg);
3112 PUT32(sc, RADEON_DP_CNTL,
3116 PUT32(sc, RADEON_SRC_X_Y, 0);
3118 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd);
3119 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h);
3212 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
3221 PUT32(sc, RADEON_DP_CNTL,
3225 PUT32(sc, RADEON_SRC_X_Y, 0);
3226 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd);
3227 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h);
3262 PUT32(sc, RADEON_HOST_DATA0, pixel);
3315 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
3324 PUT32(sc, RADEON_DP_CNTL,
3328 PUT32(sc, RADEON_SRC_X_Y, 0);
3329 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y);
3330 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he);
3367 PUT32(sc, RADEON_HOST_DATA0, latch);
3387 PUT32(sc, RADEON_HOST_DATA0, latch);
3545 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
3551 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color);
3552 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff);
3553 PUT32(sc, RADEON_DP_CNTL,
3556 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx);
3557 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height));
3597 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
3604 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff);
3605 PUT32(sc, RADEON_DP_CNTL, dir);
3606 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx);
3607 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx);
3608 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height));
3667 PUT32(sc, RADEON_SC_TOP_LEFT, 0);
3668 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff);
3678 PUT32(sc, RADEON_RB3D_CNTL, 0);
3707 PUT32(sc, RADEON_SURFACE_CNTL, RADEON_SURF_TRANSLATION_DIS);
3711 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0);
3731 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, pitch);
3732 PUT32(sc, RADEON_DST_PITCH_OFFSET, pitch);
3733 PUT32(sc, RADEON_SRC_PITCH_OFFSET, pitch);
3739 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT,
3743 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
3750 PUT32(sc, RADEON_DST_LINE_START, 0);
3751 PUT32(sc, RADEON_DST_LINE_END, 0);
3752 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff);
3753 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0);
3754 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff);
3755 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0);
3756 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff);
3757 PUT32(sc, RADEON_SC_TOP_LEFT, 0);
3758 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff);
3759 PUT32(sc, RADEON_AUX_SC_CNTL, 0);
3784 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm |
3789 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0);
3796 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm |
3804 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm &
3814 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET);
3816 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc);
3819 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm);
3821 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex);
4103 PUT32(sc, AVIVO_D1CUR_SIZE, 0x003f003f);
4179 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) +
4182 PUT32(sc, offset, (dp->rd_curoff + coff) | lock);
4183 PUT32(sc, hvoff, (xoff << 16) | (yoff) | lock);
4185 PUT32(sc, hvpos, (x << 16) | y);
4243 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]);
4244 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]);
Indexes created Sun Oct 19 19:09:49 GMT 2025