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Lines Matching refs:SET32

695 			SET32(sc, RADEON_DAC_CNTL2,
766 	SET32(sc, RADEON_FP_GEN_CNTL,
780 		SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2);
1044 		SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON);
2320 	SET32(sc, RADEON_CRTC_EXT_CNTL,
2606 			SET32(sc, AVIVO_D1CRTC_CONTROL, AVIVO_CRTC_EN);
2607 			SET32(sc, AVIVO_D2CRTC_CONTROL, AVIVO_CRTC_EN);
2627 			SET32(sc, reg, mask);
2631 			SET32(sc, fpreg, fpval);
2909 				SET32(sc, RADEON_DAC_CNTL2,
3644 		SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL);
3649 		SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 
3690 		SET32(sc, RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
3691 		SET32(sc, R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG);
3692 		SET32(sc, R300_RB2D_DSTCACHE_MODE, R300_DC_AUTOFLUSH_ENABLE |
3794 		SET32(sc, RADEON_RB2D_DSTCACHE_MODE, R300_DC_DC_DISABLE_IGNORE_PE);
4102 		SET32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK);
4200 			SET32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK);
4218 			SET32(dp->rd_softc, gencntl, bit);
4259 				SET32(sc, AVIVO_D2CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK);
4261 				SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK);
4264 				SET32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK);
4266 				SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK);