Lines Matching refs:sc_wdcdev
99 sc->sc_wdcdev.sc_atac.atac_dev = self;
131 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
136 sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS;
138 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
139 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
141 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
142 sc->sc_wdcdev.irqack = pciide_irqack;
143 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
144 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
147 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
148 sc->sc_wdcdev.sc_atac.atac_nchannels = 4;
149 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
152 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
153 sc->sc_wdcdev.wdc_maxdrives = 1;
155 wdc_allocate_regs(&sc->sc_wdcdev);
159 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
165 svwsata_intr, sc, device_xname(sc->sc_wdcdev.sc_atac.atac_dev));
167 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
171 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
182 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
199 sc->sc_wdcdev.dma_arg = sc;
200 sc->sc_wdcdev.dma_init = pciide_dma_init;
201 sc->sc_wdcdev.dma_start = pciide_dma_start;
202 sc->sc_wdcdev.dma_finish = pciide_dma_finish;
204 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
258 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
267 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
277 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
293 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
301 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
309 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
345 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
Indexes created Mon Oct 20 05:10:11 GMT 2025