Cross Reference: /src/sys/dev/pci/ubsec.c

Lines Matching defs:mcr
673 			 * the same MCR, and complete them too, they must be
699 		struct ubsec_mcr *mcr;
708 			mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr;
712 				flags = htole16(mcr->mcr_flags);
714 				flags = mcr->mcr_flags;
735 		struct ubsec_mcr *mcr;
744 			mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr;
747 			flags = htole16(mcr->mcr_flags);
822 	 * Decide how many ops to combine in a single MCR.  We cannot
2057 	struct ubsec_mcr *mcr;
2082 	mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr;
2085 	mcr->mcr_pkts = htole16(1);
2086 	mcr->mcr_flags = 0;
2087 	mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr);
2088 	mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0;
2089 	mcr->mcr_ipktbuf.pb_len = 0;
2090 	mcr->mcr_reserved = mcr->mcr_pktlen = 0;
2091 	mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr);
2092 	mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) &
2094 	mcr->mcr_opktbuf.pb_next = 0;
2305 	 * Free header MCR
2419 	struct ubsec_mcr *mcr;
2467 	mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2524 	mcr->mcr_pkts = htole16(1);
2525 	mcr->mcr_flags = 0;
2526 	mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2527 	mcr->mcr_reserved = 0;
2528 	mcr->mcr_pktlen = 0;
2530 	mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2531 	mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2532 	mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2534 	mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2535 	mcr->mcr_opktbuf.pb_next = 0;
2536 	mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2540 	if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2542 		    letoh32(mcr->mcr_opktbuf.pb_addr));
2543 	if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2545 		    letoh32(mcr->mcr_opktbuf.pb_len));
2560 		ubsec_dump_mcr(mcr);
2566 	 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2624 	struct ubsec_mcr *mcr;
2673 	mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2730 	mcr->mcr_pkts = htole16(1);
2731 	mcr->mcr_flags = 0;
2732 	mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2733 	mcr->mcr_reserved = 0;
2734 	mcr->mcr_pktlen = 0;
2736 	mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2737 	mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2738 	mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2740 	mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2741 	mcr->mcr_opktbuf.pb_next = 0;
2742 	mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2746 	if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2748 		    letoh32(mcr->mcr_opktbuf.pb_addr));
2749 	if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2751 		    letoh32(mcr->mcr_opktbuf.pb_len));
2765 		ubsec_dump_mcr(mcr);
2771 	 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2825 	struct ubsec_mcr *mcr;
2878 	mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr;
2942 	mcr->mcr_pkts = htole16(1);
2943 	mcr->mcr_flags = 0;
2944 	mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr);
2945 	mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr);
2946 	mcr->mcr_ipktbuf.pb_next = 0;
2947 	mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size);
2948 	mcr->mcr_reserved = 0;
2949 	mcr->mcr_pktlen = htole16(msglen);
2950 	mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr);
2951 	mcr->mcr_opktbuf.pb_next = 0;
2952 	mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size);
2973 	 * ubsec_feed2 will sync mcr and ctx, we just need to sync
3045 ubsec_dump_mcr(struct ubsec_mcr *mcr)
3050 	printf("MCR:\n");
3052 	    letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags));
3053 	ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp;
3054 	for (i = 0; i < letoh16(mcr->mcr_pkts); i++) {
3064 	printf("END MCR\n");
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