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Lines Matching refs:VIASR

288 	val = uni_rd(sc, VIASR, SR30);
290 	val = uni_rd(sc, VIASR, SR39);
651 		bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIASR, i);
652 		bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIASR + 1,
678 	uni_wr_mask(sc, VIASR, SR16, 0x00, BIT6);
714 	uni_wr_mask(sc, VIASR, SR01, 0, BIT5);
720 	uni_wr_mask(sc, VIASR, SR01, 0x20, BIT5);
947 			uni_wr_mask(sc, VIASR, cridx, data, regmask);
1000 		    VIASR);
1041 		uni_load_reg(sc, val, regnum, reg, VIASR);
1047 		uni_load_reg(sc, val, regnum, reg, VIASR);
1053 		uni_load_reg(sc, val, regnum, reg, VIASR);
1059 		uni_load_reg(sc, val, regnum, reg, VIASR);
1078 			uni_wr_mask(sc, VIASR, SR15, 0xae, 0xfe);
1081 			uni_wr_mask(sc, VIASR, SR15, 0xb6, 0xfe);
1084 			uni_wr_mask(sc, VIASR, SR15, 0x22, 0xfe);
1126 		uni_wr(sc, VIASR, SR44, clk / 0x10000);
1127 		uni_wr(sc, VIASR, SR45, (clk & 0xffff) / 0x100);
1128 		uni_wr(sc, VIASR, SR46, clk % 0x100);
1142 		uni_wr_mask(sc, VIASR, SR40, 0x02, BIT1);
1143 		uni_wr_mask(sc, VIASR, SR40, 0x00, BIT1);
1161 	uni_wr_mask(sc, VIASR, SR1A, 0x00, BIT0);
1162 	uni_wr_mask(sc, VIASR, SR18, 0x00, BIT7+BIT6);
1167 	uni_wr_mask(sc, VIASR, SR18, 0xc0, BIT7+BIT6);