Lines Matching defs:cfe
90 struct pcmcia_config_entry *cfe, *ncfe;
94 for (cfe = SIMPLEQ_FIRST(&pf->cfe_head); cfe != NULL;
95 cfe = ncfe) {
96 ncfe = SIMPLEQ_NEXT(cfe, cfe_list);
97 free(cfe, M_DEVBUF);
542 struct pcmcia_config_entry *cfe;
624 cfe, &pf->cfe_head, cfe_list) {
626 device_xname(sc->dev), pf->number, cfe->number);
628 switch (cfe->iftype) {
640 printf("; irq mask %x", cfe->irqmask);
642 if (cfe->num_iospace) {
643 printf("; iomask %lx, iospace", cfe->iomask);
645 for (i = 0; i < cfe->num_iospace; i++) {
646 printf(" %lx", cfe->iospace[i].start);
647 if (cfe->iospace[i].length)
649 cfe->iospace[i].start +
650 cfe->iospace[i].length - 1);
653 if (cfe->num_memspace) {
656 for (i = 0; i < cfe->num_memspace; i++) {
658 cfe->memspace[i].cardaddr);
659 if (cfe->memspace[i].length)
661 cfe->memspace[i].cardaddr +
662 cfe->memspace[i].length - 1);
663 if (cfe->memspace[i].hostaddr)
665 cfe->memspace[i].hostaddr);
668 if (cfe->maxtwins)
669 printf("; maxtwins %d", cfe->maxtwins);
673 if (cfe->flags & PCMCIA_CFE_MWAIT_REQUIRED)
675 if (cfe->flags & PCMCIA_CFE_RDYBSY_ACTIVE)
677 if (cfe->flags & PCMCIA_CFE_WP_ACTIVE)
679 if (cfe->flags & PCMCIA_CFE_BVD_ACTIVE)
681 if (cfe->flags & PCMCIA_CFE_IO8)
683 if (cfe->flags & PCMCIA_CFE_IO16)
685 if (cfe->flags & PCMCIA_CFE_IRQSHARE)
687 if (cfe->flags & PCMCIA_CFE_IRQPULSE)
689 if (cfe->flags & PCMCIA_CFE_IRQLEVEL)
691 if (cfe->flags & PCMCIA_CFE_POWERDOWN)
693 if (cfe->flags & PCMCIA_CFE_READONLY)
695 if (cfe->flags & PCMCIA_CFE_AUDIO)
1039 /* reset the default cfe for each cfe list */
1052 struct pcmcia_config_entry *cfe;
1088 cfe = malloc(sizeof(*cfe), M_DEVBUF, M_WAITOK);
1089 *cfe = *state->default_cfe;
1091 SIMPLEQ_INSERT_TAIL(&state->pf->cfe_head, cfe, cfe_list);
1093 cfe->number = num;
1101 state->default_cfe = cfe;
1118 cfe = state->default_cfe;
1134 cfe->flags &= ~(PCMCIA_CFE_MWAIT_REQUIRED
1139 cfe->flags |= PCMCIA_CFE_MWAIT_REQUIRED;
1141 cfe->flags |= PCMCIA_CFE_RDYBSY_ACTIVE;
1143 cfe->flags |= PCMCIA_CFE_WP_ACTIVE;
1145 cfe->flags |= PCMCIA_CFE_BVD_ACTIVE;
1146 cfe->iftype = reg & PCMCIA_TPCE_IF_IFTYPE;
1207 cfe->flags &=
1210 cfe->flags |= PCMCIA_CFE_IO8;
1212 cfe->flags |= PCMCIA_CFE_IO16;
1213 cfe->iomask =
1220 cfe->num_iospace = 1 + (reg &
1223 if (cfe->num_iospace >
1224 (sizeof(cfe->iospace) /
1225 sizeof(cfe->iospace[0]))) {
1228 cfe->num_iospace));
1232 for (i = 0; i < cfe->num_iospace; i++) {
1235 cfe->iospace[i].start =
1239 cfe->iospace[i].start =
1244 cfe->iospace[i].start =
1249 cfe->iospace[i].start =
1257 cfe->iospace[i].length =
1261 cfe->iospace[i].length =
1266 cfe->iospace[i].length =
1271 cfe->iospace[i].length =
1276 cfe->iospace[i].length++;
1279 cfe->num_iospace = 1;
1280 cfe->iospace[0].start = 0;
1281 cfe->iospace[0].length =
1282 (1 << cfe->iomask);
1294 cfe->flags &= ~(PCMCIA_CFE_IRQSHARE
1298 cfe->flags |= PCMCIA_CFE_IRQSHARE;
1300 cfe->flags |= PCMCIA_CFE_IRQPULSE;
1302 cfe->flags |= PCMCIA_CFE_IRQLEVEL;
1310 cfe->irqmask =
1314 cfe->irqmask =
1331 cfe->num_memspace = 0;
1336 cfe->num_memspace = 1;
1337 cfe->memspace[0].length = 256 *
1340 cfe->memspace[0].cardaddr = 0;
1341 cfe->memspace[0].hostaddr = 0;
1345 cfe->num_memspace = 1;
1346 cfe->memspace[0].length = 256 *
1349 cfe->memspace[0].cardaddr = 256 *
1352 cfe->memspace[0].hostaddr =
1353 cfe->memspace[0].cardaddr;
1360 cfe->num_memspace = (reg & PCMCIA_TPCE_MS_COUNT)
1363 if (cfe->num_memspace >
1364 (sizeof(cfe->memspace) /
1365 sizeof(cfe->memspace[0]))) {
1367 cfe->num_memspace));
1383 DPRINTF(("cfe memspace "
1387 for (i = 0; i < cfe->num_memspace; i++) {
1389 cfe->memspace[i].length = 256 *
1394 cfe->memspace[i].length = 0;
1396 if (cfe->memspace[i].length == 0) {
1397 DPRINTF(("cfe->memspace"
1402 cfe->memspace[i].cardaddr =
1408 cfe->memspace[i].cardaddr = 0;
1411 cfe->memspace[i].hostaddr =
1417 cfe->memspace[i].hostaddr = 0;
1432 cfe->flags &= ~(PCMCIA_CFE_POWERDOWN
1436 cfe->flags |= PCMCIA_CFE_POWERDOWN;
1438 cfe->flags |= PCMCIA_CFE_READONLY;
1440 cfe->flags |= PCMCIA_CFE_AUDIO;
1441 cfe->maxtwins = reg & PCMCIA_TPCE_MI_MAXTWINS;
Indexes created Wed Oct 01 12:09:54 GMT 2025