Cross Reference: /src/sys/dev/podulebus/hcsc.c

Lines Matching defs:ncr_sc
145 	struct ncr5380_softc *ncr_sc = &sc->sc_ncr5380;
152 	ncr_sc->sc_dev = self;
153 	ncr_sc->sc_min_dma_len = 0;
154 	ncr_sc->sc_no_disconnect = 0;
155 	ncr_sc->sc_parity_disable = 0;
157 	ncr_sc->sc_dma_alloc = NULL;
158 	ncr_sc->sc_dma_free = NULL;
159 	ncr_sc->sc_dma_poll = NULL;
160 	ncr_sc->sc_dma_setup = NULL;
161 	ncr_sc->sc_dma_start = NULL;
162 	ncr_sc->sc_dma_eop = NULL;
163 	ncr_sc->sc_dma_stop = NULL;
164 	ncr_sc->sc_intr_on = NULL;
165 	ncr_sc->sc_intr_off = NULL;
168 	ncr_sc->sc_regt = pa->pa_fast_t;
169 	bus_space_map(ncr_sc->sc_regt,
171 	    &ncr_sc->sc_regh);
172 	ncr_sc->sci_r0 = 0;
173 	ncr_sc->sci_r1 = 1;
174 	ncr_sc->sci_r2 = 2;
175 	ncr_sc->sci_r3 = 3;
176 	ncr_sc->sci_r4 = 4;
177 	ncr_sc->sci_r5 = 5;
178 	ncr_sc->sci_r6 = 6;
179 	ncr_sc->sci_r7 = 7;
182 	ncr_sc->sci_r0 = iobase + 0;
183 	ncr_sc->sci_r1 = iobase + 4;
184 	ncr_sc->sci_r2 = iobase + 8;
185 	ncr_sc->sci_r3 = iobase + 12;
186 	ncr_sc->sci_r4 = iobase + 16;
187 	ncr_sc->sci_r5 = iobase + 20;
188 	ncr_sc->sci_r6 = iobase + 24;
189 	ncr_sc->sci_r7 = iobase + 28;
195 	ncr_sc->sc_rev = NCR_VARIANT_DP8490;
197 	ncr_sc->sc_pio_in = hcsc_pdma_in;
198 	ncr_sc->sc_pio_out = hcsc_pdma_out;
201 	ncr_sc->sc_channel.chan_id = 7;
205 	    BOOTOPT_TYPE_INT, &ncr_sc->sc_channel.chan_id);
206 	ncr_sc->sc_adapter.adapt_minphys = minphys;
208 	aprint_normal(": host ID %d\n", ncr_sc->sc_channel.chan_id);
215 	ncr5380_attach(ncr_sc);
265 hcsc_pdma_in(struct ncr5380_softc *ncr_sc, int phase, int datalen,
268 	struct hcsc_softc *sc = (struct hcsc_softc *)ncr_sc;
275 	NCR5380_WRITE(ncr_sc, sci_mode,
276 	    NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA);
277 	NCR5380_WRITE(ncr_sc, sci_irecv, 0);
282 		if (hcsc_ready(ncr_sc) == 0)
289 	hcsc_wait_not_req(ncr_sc);
292 	SCI_CLR_INTR(ncr_sc);
293 	NCR5380_WRITE(ncr_sc, sci_mode,
294 	    NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA);
300 hcsc_pdma_out(struct ncr5380_softc *ncr_sc, int phase, int datalen,
303 	struct hcsc_softc *sc = (struct hcsc_softc *)ncr_sc;
309 	icmd = NCR5380_READ(ncr_sc, sci_icmd) & SCI_ICMD_RMASK;
310 	NCR5380_WRITE(ncr_sc, sci_icmd, icmd | SCI_ICMD_DATA);
311 	NCR5380_WRITE(ncr_sc, sci_mode,
312 	    NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA);
313 	NCR5380_WRITE(ncr_sc, sci_dma_send, 0);
316 	if (hcsc_ready(ncr_sc) == 0)
336 			if (hcsc_ready(ncr_sc) == 0) {
344 		if (hcsc_ready(ncr_sc) == 0) {
355 		if ((NCR5380_READ(ncr_sc, sci_csr)
364 		    device_xname(ncr_sc->sc_dev));
366 	hcsc_wait_not_req(ncr_sc);
368 	SCI_CLR_INTR(ncr_sc);
369 	NCR5380_WRITE(ncr_sc, sci_mode,
370 	    NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA);
371 	NCR5380_WRITE(ncr_sc, sci_icmd, icmd);
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