Cross Reference: /src/sys/dev/podulebus/oak.c

Lines Matching defs:ncr_sc
140 	struct ncr5380_softc *ncr_sc = &sc->sc_ncr5380;
147 	ncr_sc->sc_dev = self;
148 	ncr_sc->sc_flags |= NCR5380_FORCE_POLLING;
149 	ncr_sc->sc_min_dma_len = 0;
150 	ncr_sc->sc_no_disconnect = 0xff;
151 	ncr_sc->sc_parity_disable = 0;
153 	ncr_sc->sc_dma_alloc = NULL;
154 	ncr_sc->sc_dma_free = NULL;
155 	ncr_sc->sc_dma_poll = NULL;
156 	ncr_sc->sc_dma_setup = NULL;
157 	ncr_sc->sc_dma_start = NULL;
158 	ncr_sc->sc_dma_eop = NULL;
159 	ncr_sc->sc_dma_stop = NULL;
160 	ncr_sc->sc_intr_on = NULL;
161 	ncr_sc->sc_intr_off = NULL;
164 	ncr_sc->sc_regt = pa->pa_mod_t;
165 	bus_space_map(ncr_sc->sc_regt, pa->pa_mod_base, 8, 0,
166 	    &ncr_sc->sc_regh);
167 	ncr_sc->sci_r0 = 0;
168 	ncr_sc->sci_r1 = 1;
169 	ncr_sc->sci_r2 = 2;
170 	ncr_sc->sci_r3 = 3;
171 	ncr_sc->sci_r4 = 4;
172 	ncr_sc->sci_r5 = 5;
173 	ncr_sc->sci_r6 = 6;
174 	ncr_sc->sci_r7 = 7;
177 	ncr_sc->sci_r0 = iobase + 0;
178 	ncr_sc->sci_r1 = iobase + 4;
179 	ncr_sc->sci_r2 = iobase + 8;
180 	ncr_sc->sci_r3 = iobase + 12;
181 	ncr_sc->sci_r4 = iobase + 16;
182 	ncr_sc->sci_r5 = iobase + 20;
183 	ncr_sc->sci_r6 = iobase + 24;
184 	ncr_sc->sci_r7 = iobase + 28;
190 	ncr_sc->sc_rev = NCR_VARIANT_NCR5380;
192 	ncr_sc->sc_pio_in = ncr5380_pio_in;
193 	ncr_sc->sc_pio_out = ncr5380_pio_out;
196 	ncr_sc->sc_channel.chan_id = 7;
200 	    BOOTOPT_TYPE_INT, &ncr_sc->sc_channel.chan_id);
201 	ncr_sc->sc_adapter.adapt_minphys = minphys;
204 	    ncr_sc->sc_channel.chan_id);
206 	ncr5380_attach(ncr_sc);
245 	struct oak_softc *sc = (void *)ncr_sc;
258 	    device_xname(ncr_sc->sc_dev), status);
280 oak_pdma_in(struct ncr5380_softc *ncr_sc, int phase, int datalen,
283 	struct oak_softc *sc = (void *)ncr_sc;
290 	NCR5380_WRITE(ncr_sc, sci_mode,
291 	    NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA);
292 	NCR5380_WRITE(ncr_sc, sci_irecv, 0);
297 		if (oak_ready(ncr_sc) == 0)
306 	oak_wait_not_req(ncr_sc);
309 	SCI_CLR_INTR(ncr_sc);
310 	NCR5380_WRITE(ncr_sc, sci_mode,
311 	    NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA);
317 oak_pdma_out(struct ncr5380_softc *ncr_sc, int phase, int datalen,
320 	struct oak_softc *sc = (struct oak_softc *)ncr_sc;
326 	icmd = NCR5380_READ(ncr_sc, sci_icmd) & SCI_ICMD_RMASK;
327 	NCR5380_WRITE(ncr_sc, sci_icmd, icmd | SCI_ICMD_DATA);
328 	NCR5380_WRITE(ncr_sc, sci_mode,
329 	    NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA);
330 	NCR5380_WRITE(ncr_sc, sci_dma_send, 0);
333 	if (oak_ready(ncr_sc) == 0)
355 			if (oak_ready(ncr_sc) == 0) {
363 		if (oak_ready(ncr_sc) == 0) {
375 		if ((NCR5380_READ(ncr_sc, sci_csr)
384 		    device_xname(ncr_sc->sc_dev));
386 	oak_wait_not_req(ncr_sc);
388 	SCI_CLR_INTR(ncr_sc);
389 	NCR5380_WRITE(ncr_sc, sci_mode,
390 	    NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA);
391 	NCR5380_WRITE(ncr_sc, sci_icmd, icmd);
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