Lines Matching refs:cd
264 cd1400_write_ccr(struct cd1400 *cd, u_char cmd)
266 while( cd1400_read_reg(cd, CD1400_CCR) )
269 cd1400_write_reg(cd, CD1400_CCR, cmd);
276 cd1400_read_reg(struct cd1400 *cd, int reg)
278 return(cd->cd_reg[reg]);
285 cd1400_write_reg(struct cd1400 *cd, int reg, u_char value)
287 cd->cd_reg[reg] = value;
294 cd1400_enable_transmitter(struct cd1400 *cd, int channel)
299 cd1400_write_reg(cd, CD1400_CAR, channel);
300 srer = cd1400_read_reg(cd, CD1400_SRER);
302 cd1400_write_reg(cd, CD1400_SRER, srer);
426 struct cd1400 *cd = &sc->ms_cd1400[chip];
428 cd->cd_clock = cd_clock;
429 cd->cd_reg = (char *)bus_space_vaddr(sa->sa_bustag, bh) +
434 cd->cd_chiprev = cd1400_read_reg(cd, CD1400_GFRCR);
438 cd->cd_reg, cd->cd_chiprev, cd->cd_clock));
441 cd1400_write_reg(cd, CD1400_GFRCR, 0x00);
444 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FULLRESET);
447 while( cd1400_read_reg(cd, CD1400_GFRCR) != cd->cd_chiprev )
451 cd1400_write_reg(cd, CD1400_PPR,
452 ((cd->cd_clock * 1000000 / CD1400_PPR_PRESCALER + 500) / 1000));
460 cd1400_write_reg(cd, CD1400_GCR, CD1400_GCR_PARALLEL);
461 cd->cd_parmode = 1;
467 struct cd1190 *cd = &sc->ms_cd1190[chip];
469 cd->cd_reg = (char *)bus_space_vaddr(sa->sa_bustag, bh) +
474 device_xname(self), chip, cd->cd_reg);
510 struct cd1400 *cd;
530 cd = mbpp->mp_cd1400;
533 n_chars = cd1400_read_reg(cd, CD1400_RDCR);
540 *mbpp->mp_ptr = cd1400_read_reg(cd,CD1400_RDSR);
549 cd = mtty->mp_cd1400;
552 line_stat = cd1400_read_reg(cd, CD1400_RDSR);
556 n_chars = cd1400_read_reg(cd, CD1400_RDCR);
562 *ptr++ = cd1400_read_reg(cd, CD1400_RDSR);
577 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */
589 * Handle CD (LC2+1Sp = DSR) changes.
592 cd = mtty->mp_cd1400;
593 msvr = cd1400_read_reg(cd, CD1400_MSVR2);
594 carrier = ISSET(msvr, cd->cd_parmode ? CD1400_MSVR2_DSR : CD1400_MSVR2_CD);
602 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */
614 cd = mbpp->mp_cd1400;
622 cd1400_write_reg(cd, CD1400_TDR,
635 cd1400_write_reg(cd, CD1400_SRER, 0);
643 cd = mtty->mp_cd1400;
650 cd1400_write_reg(cd, CD1400_TDR, 0);
651 cd1400_write_reg(cd, CD1400_TDR, 0x81);
658 cd1400_write_reg(cd, CD1400_TDR, 0);
659 cd1400_write_reg(cd, CD1400_TDR, 0x83);
677 cd1400_write_reg(cd, CD1400_TDR, ch);
681 cd1400_write_reg(cd, CD1400_TDR, ch);
693 srer = cd1400_read_reg(cd, CD1400_SRER);
695 cd1400_write_reg(cd, CD1400_SRER, srer);
703 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */
776 dprintf(("%s%x: cd %s\n", device_xname(mtty->ms_dev),
898 struct cd1400 *cd;
934 cd = mp->mp_cd1400;
935 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel);
936 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET);
939 cd1400_write_reg(cd, CD1400_LIVR, port << 4 );
948 cd1400_write_reg(cd, CD1400_SRER,
1002 struct cd1400 *cd = mp->mp_cd1400;
1009 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel);
1010 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET);
1211 * not available on the LC2+1Sp card (used as CD)
1218 struct cd1400 *cd = mp->mp_cd1400;
1224 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel);
1232 msvr = cd1400_read_reg(cd, CD1400_MSVR1);
1235 msvr = cd1400_read_reg(cd, CD1400_MSVR2);
1239 if( msvr & CD1400_MSVR2_DSR ) bits |= (cd->cd_parmode ? TIOCM_CD : TIOCM_DSR);
1240 if( msvr & CD1400_MSVR2_CD ) bits |= (cd->cd_parmode ? 0 : TIOCM_CD);
1246 cd1400_write_reg(cd, CD1400_MSVR2, ((bits & TIOCM_RTS) ? CD1400_MSVR2_DTR : 0));
1248 cd1400_write_reg(cd, CD1400_MSVR1, ((bits & TIOCM_DTR) ? CD1400_MSVR1_RTS : 0));
1254 cd1400_write_reg(cd, CD1400_MSVR2, CD1400_MSVR2_DTR);
1257 cd1400_write_reg(cd, CD1400_MSVR1, CD1400_MSVR1_RTS);
1263 cd1400_write_reg(cd, CD1400_MSVR2, 0);
1266 cd1400_write_reg(cd, CD1400_MSVR1, 0);
1284 struct cd1400 *cd = mp->mp_cd1400;
1289 if( t->c_ospeed && cd1400_compute_baud(t->c_ospeed, cd->cd_clock, &tcor, &tbpr) )
1292 if( t->c_ispeed && cd1400_compute_baud(t->c_ispeed, cd->cd_clock, &rcor, &rbpr) )
1301 /* cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); */
1305 cd1400_write_reg(cd, CD1400_TCOR, tcor);
1306 cd1400_write_reg(cd, CD1400_TBPR, tbpr);
1311 cd1400_write_reg(cd, CD1400_RCOR, rcor);
1312 cd1400_write_reg(cd, CD1400_RBPR, rbpr);
1317 cd1400_write_ccr(cd, opt);
1348 cd1400_write_reg(cd, CD1400_COR1, opt);
1356 cd1400_write_reg(cd, CD1400_COR2, opt);
1358 cd1400_write_reg(cd, CD1400_COR3, MTTY_RX_FIFO_THRESHOLD);
1360 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR1 | CD1400_CCR_COR2 | CD1400_CCR_COR3);
1362 cd1400_write_reg(cd, CD1400_COR4, CD1400_COR4_PFO_EXCEPTION);
1363 cd1400_write_reg(cd, CD1400_COR5, 0);
1373 if( cd->cd_parmode ) {
1381 cd1400_write_reg(cd, CD1400_MCOR1, mcor1);
1382 cd1400_write_reg(cd, CD1400_MCOR2, mcor2);
1385 cd1400_write_reg(cd, CD1400_RTPR, 2);
1475 struct cd1400 *cd = mp->mp_cd1400;
1479 cd1400_write_reg(cd, CD1400_CAR, 0);
1480 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET);
1481 cd1400_write_reg(cd, CD1400_LIVR, (1<<3));
1689 struct cd1400 *cd = mp->mp_cd1400;
1697 if( cd ) {
1698 cd1400_write_reg(cd, CD1400_CAR, 0);
1701 cd1400_write_reg(cd, CD1400_TBPR, 10);
1704 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN);
1705 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_TXRDY);
1712 if( cd ) {
1713 cd1400_write_reg(cd, CD1400_CAR, 0);
1716 cd1400_write_reg(cd, CD1400_SRER, 0);
1717 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTDIS);
1720 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FTF);
1732 struct cd1400 *cd = mp->mp_cd1400;
1740 if( cd ) {
1743 cd1400_write_reg(cd, CD1400_CAR, 0);
1746 if (cd1400_compute_baud(100000, cd->cd_clock, &rcor, &rbpr)) {
1750 cd1400_write_reg(cd, CD1400_RCOR, rcor);
1751 cd1400_write_reg(cd, CD1400_RBPR, rbpr);
1754 cd1400_write_reg(cd, CD1400_COR3, MBPP_RX_FIFO_THRESHOLD);
1755 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR3);
1758 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVEN);
1759 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_RXDATA);
1766 if( cd ) {
1767 cd1400_write_reg(cd, CD1400_CAR, 0);
1770 cd1400_write_reg(cd, CD1400_SRER, 0);
1771 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVDIS);
Indexes created Sun Oct 19 19:09:49 GMT 2025