Lines Matching defs:socket
47 #define STP4020_NWIN 3 /* number of windows per socket */
50 * Socket control registers.
52 * Each PCMCIA socket has two interface control registers and two interface
57 * Socket Interface Control register 0
101 * Socket Interface Control register 1
116 * should be switched onto Vpp for this socket.
142 * Socket Interface Status register 0
145 * the socket is configured as MEMORY-ONLY or MEMORY & I/O:
146 * mo: valid only if the socket is in memory-only mode
147 * io: valid only if the socket is in memory and I/O mode.
190 * Socket Interface Status register 1
202 * Socket window control/status register definitions.
205 * "Each PCMCIA socket has three windows associated with it; each of
264 * For each socket, there is one stp4020_socket_csr_t structure, which
265 * refers to all the registers for that socket. That structure is
267 * that control overall socket operation.
282 * per-socket CSR structure
286 volatile ushort_t ctl0; /* socket control register 0 */
287 volatile ushort_t ctl1; /* socket control register 1 */
288 volatile ushort_t stat0; /* socket status register 0 */
289 volatile ushort_t stat1; /* socket status register 1 */
297 struct stp4020_socket_csr_t socket[STP4020_NSOCK]; /* socket CSRs */
305 /* Relative socket control & status register offsets */
315 /* Socket control and status register offsets */
321 /* Window control and status registers; one set per socket */
Indexes created Wed Oct 15 07:09:58 GMT 2025