Lines Matching refs:ISSET
159 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE))
165 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
180 ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? ocr : 0, &card_ocr);
182 if (ISSET(sc->sc_flags, SMF_SD_MODE) &&
183 !ISSET(sc->sc_flags, SMF_IO_MODE)) {
189 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) {
200 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
223 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
224 if (ISSET(sc->sc_flags, SMF_SD_MODE)) {
247 if (ISSET(sc->sc_flags, SMF_SD_MODE) && ISSET(new_ocr, MMC_OCR_S18A)) {
348 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) &&
359 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) {
378 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
397 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE))
401 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE))
453 if (ISSET(sc->sc_flags, SMF_SD_MODE)) {
521 if (ISSET(sc->sc_flags, SMF_SD_MODE)) {
590 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
600 if (ISSET(sc->sc_flags, SMF_SD_MODE))
636 cmd.c_arg = !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ?
641 if (ISSET(sc->sc_flags, SMF_SD_MODE)) {
651 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
652 if (!ISSET(MMC_SPI_R1(cmd.c_resp), R1_SPI_IDLE))
655 if (ISSET(MMC_R3(cmd.c_resp), MMC_OCR_MEM_READY) ||
665 !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
691 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
745 if (ISSET(sc->sc_flags, SMF_UHS_MODE)) {
746 if (ISSET(sc->sc_caps, SMC_CAPS_UHS_SDR104) &&
747 ISSET(support_func, 1 << SD_ACCESS_MODE_SDR104)) {
750 if (ISSET(sc->sc_caps, SMC_CAPS_UHS_DDR50) &&
751 ISSET(support_func, 1 << SD_ACCESS_MODE_DDR50)) {
754 if (ISSET(sc->sc_caps, SMC_CAPS_UHS_SDR50) &&
755 ISSET(support_func, 1 << SD_ACCESS_MODE_SDR50)) {
759 if (ISSET(sc->sc_caps, SMC_CAPS_SD_HIGHSPEED) &&
760 ISSET(support_func, 1 << SD_ACCESS_MODE_SDR25)) {
771 if (ISSET(sc->sc_flags, SMF_SD_MODE)) {
772 if (!ISSET(sc->sc_flags, SMF_UHS_MODE))
825 if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE) &&
826 ISSET(sf->scr.bus_width, SCR_SD_BUS_WIDTHS_4BIT)) {
839 ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) {
855 if (!ISSET(sc->sc_flags, SMF_UHS_MODE) && support_func & 0x1c) {
937 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) && sf->scr.support_cmd48) {
995 if (ISSET(sc->sc_caps, SMC_CAPS_MMC_HS200) &&
998 } else if (ISSET(sc->sc_caps, SMC_CAPS_MMC_DDR52) &&
1013 if (ISSET(sc->sc_caps, SMC_CAPS_8BIT_MODE)) {
1016 } else if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE)) {
1042 !ISSET(sc->sc_caps, SMC_CAPS_MMC_HIGHSPEED)) {
1198 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
1225 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
1259 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1288 if (ISSET(sc->sc_caps, SMC_CAPS_DMA))
1293 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1302 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1375 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1404 if (ISSET(sc->sc_caps, SMC_CAPS_DMA))
1409 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1418 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1470 if (ISSET(perf_enhance, SSR_PERFORMANCE_ENHANCE_CACHE)) {
1490 if (ISSET(perf_enhance, SSR_PERFORMANCE_ENHANCE_CACHE))
1492 if (ISSET(perf_enhance, SSR_PERFORMANCE_ENHANCE_HOST_MAINT|
1597 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1630 if (ISSET(sc->sc_caps, SMC_CAPS_DMA))
1635 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1647 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1670 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1700 if (ISSET(sc->sc_caps, SMC_CAPS_DMA))
1705 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1717 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1740 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1774 if (ISSET(sc->sc_caps, SMC_CAPS_DMA))
1779 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1787 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1810 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA));
1829 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE))
1867 !ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH))
1876 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1906 if (ISSET(sc->sc_caps, SMC_CAPS_DMA))
1911 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1920 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1962 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE))
1970 if (ISSET(MMC_R1(cmd.c_resp), MMC_R1_SWITCH_ERROR)) {
1975 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA));
2023 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA));
2110 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
2123 if (!ISSET(sf->flags, SFF_SDHC))
2126 if (ISSET(sf->flags, SFF_SDHC))
2128 if (ISSET(sc->sc_caps, SMC_CAPS_DMA))
2146 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) {
2158 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
2162 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE))
2169 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA));
2186 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) {
2191 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
2213 && !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) {
2249 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA));
2337 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
2344 if (ISSET(sc->sc_flags, SMF_SD_MODE) && nblk > 1) {
2362 if (!ISSET(sf->flags, SFF_SDHC))
2365 if (ISSET(sf->flags, SFF_SDHC))
2367 if (ISSET(sc->sc_caps, SMC_CAPS_DMA))
2385 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) {
2396 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
2400 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE))
2407 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA));
2424 if (ISSET(sc->sc_flags, SMF_SD_MODE) &&
2431 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) {
2436 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
2460 && !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) {
2493 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE))
2504 cmd.c_opcode = ISSET(sc->sc_flags, SMF_SD_MODE) ?
2507 if (!ISSET(sf->flags, SFF_SDHC))
2516 cmd.c_opcode = ISSET(sc->sc_flags, SMF_SD_MODE) ?
2519 if (!ISSET(sf->flags, SFF_SDHC))
2552 if (!ISSET(sf->flags, SFF_CACHE_ENABLED))
2558 if (ISSET(sc->sc_flags, SMF_SD_MODE)) {
Indexes created Thu Oct 23 22:10:10 GMT 2025