Lines Matching refs:sc_caps
159 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE))
165 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
180 ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? ocr : 0, &card_ocr);
200 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
223 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
348 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) &&
378 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
397 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE))
401 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE))
590 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
636 cmd.c_arg = !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ?
651 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
665 !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
691 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
746 if (ISSET(sc->sc_caps, SMC_CAPS_UHS_SDR104) &&
750 if (ISSET(sc->sc_caps, SMC_CAPS_UHS_DDR50) &&
754 if (ISSET(sc->sc_caps, SMC_CAPS_UHS_SDR50) &&
759 if (ISSET(sc->sc_caps, SMC_CAPS_SD_HIGHSPEED) &&
825 if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE) &&
937 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) && sf->scr.support_cmd48) {
995 if (ISSET(sc->sc_caps, SMC_CAPS_MMC_HS200) &&
998 } else if (ISSET(sc->sc_caps, SMC_CAPS_MMC_DDR52) &&
1013 if (ISSET(sc->sc_caps, SMC_CAPS_8BIT_MODE)) {
1016 } else if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE)) {
1042 !ISSET(sc->sc_caps, SMC_CAPS_MMC_HIGHSPEED)) {
1198 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
1225 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
1259 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1288 if (ISSET(sc->sc_caps, SMC_CAPS_DMA))
1293 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1302 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1375 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1404 if (ISSET(sc->sc_caps, SMC_CAPS_DMA))
1409 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1418 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1597 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1630 if (ISSET(sc->sc_caps, SMC_CAPS_DMA))
1635 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1647 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1670 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1700 if (ISSET(sc->sc_caps, SMC_CAPS_DMA))
1705 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1717 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1740 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1774 if (ISSET(sc->sc_caps, SMC_CAPS_DMA))
1779 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1787 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1829 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE))
1876 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1906 if (ISSET(sc->sc_caps, SMC_CAPS_DMA))
1911 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1920 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
1962 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE))
2023 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA));
2110 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
2128 if (ISSET(sc->sc_caps, SMC_CAPS_DMA))
2146 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) {
2158 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
2162 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE))
2186 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) {
2191 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
2213 && !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) {
2249 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA));
2337 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
2367 if (ISSET(sc->sc_caps, SMC_CAPS_DMA))
2385 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) {
2396 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
2400 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE))
2431 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) {
2436 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) {
2460 && !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) {
2493 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE))
Indexes created Tue Oct 21 08:09:48 GMT 2025