Lines Matching defs:otus_write
131 Static void otus_write(struct otus_softc *, uint32_t, uint32_t);
1459 otus_write(struct otus_softc *sc, uint32_t reg, uint32_t val)
2331 otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_L, lo);
2332 otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_H, hi);
2388 otus_write(sc, AR_MAC_REG_AC0_CW,
2391 otus_write(sc, AR_MAC_REG_AC1_CW,
2394 otus_write(sc, AR_MAC_REG_AC2_CW,
2397 otus_write(sc, AR_MAC_REG_AC3_CW,
2400 otus_write(sc, AR_MAC_REG_AC4_CW, /* Special TXQ. */
2405 otus_write(sc, AR_MAC_REG_AC1_AC0_AIFS,
2409 otus_write(sc, AR_MAC_REG_AC3_AC2_AIFS,
2415 otus_write(sc, AR_MAC_REG_AC1_AC0_TXOP,
2418 otus_write(sc, AR_MAC_REG_AC3_AC2_TXOP,
2464 otus_write(sc, AR_MAC_REG_SLOT_TIME, slottime << 10);
2477 otus_write(sc, AR_MAC_REG_ACK_EXTENSION, 0x40);
2478 otus_write(sc, AR_MAC_REG_RETRY_MAX, 0);
2479 otus_write(sc, AR_MAC_REG_SNIFFER, AR_MAC_REG_SNIFFER_DEFAULTS);
2480 otus_write(sc, AR_MAC_REG_RX_THRESHOLD, 0xc1f80);
2481 otus_write(sc, AR_MAC_REG_RX_PE_DELAY, 0x70);
2482 otus_write(sc, AR_MAC_REG_EIFS_AND_SIFS, 0xa144000);
2483 otus_write(sc, AR_MAC_REG_SLOT_TIME, 9 << 10);
2486 otus_write(sc, 0x1c3b2c, 0x19000000);
2489 otus_write(sc, 0x1c3b38, 0x201);
2493 otus_write(sc, AR_MAC_REG_BCN_HT1, 0x8000170);
2495 otus_write(sc, AR_MAC_REG_BACKOFF_PROTECT, 0x105);
2499 otus_write(sc, AR_MAC_REG_AMPDU_FACTOR, 0x10000a);
2502 otus_write(sc, AR_MAC_REG_FRAMETYPE_FILTER, AR_MAC_REG_FTF_DEFAULTS);
2505 otus_write(sc, 0x1c3c40, 0x1 | 1 << 30); /* XXX: was 0x1 */
2508 otus_write(sc, AR_MAC_REG_BASIC_RATE, 0x150f);
2509 otus_write(sc, AR_MAC_REG_MANDATORY_RATE, 0x150f);
2510 otus_write(sc, AR_MAC_REG_RTS_CTS_RATE, 0x10b01bb);
2513 otus_write(sc, 0x1c3694, 0x4003c1e); /* bit 26~28 otus-AM */
2516 otus_write(sc, 0x1c3600, 0x3);
2518 otus_write(sc, AR_MAC_REG_AMPDU_RX_THRESH, 0xffff);
2521 otus_write(sc, AR_MAC_REG_MISC_680, 0xf00008);
2524 otus_write(sc, AR_MAC_REG_RX_TIMEOUT, 0x0);
2527 otus_write(sc, AR_PWR_REG_CLOCK_SEL,
2531 otus_write(sc, AR_MAC_REG_TXRX_MPI, 0x110011);
2533 otus_write(sc, AR_MAC_REG_FCS_SELECT, AR_MAC_FCS_FIFO_PROT);
2536 otus_write(sc, AR_MAC_REG_TXOP_NOT_ENOUGH_INDICATION, 0x141e0f48);
2539 otus_write(sc, AR_MAC_REG_ENCRYPTION,
2546 otus_write(sc, AR_GPIO_REG_PORT_TYPE, 3);
2547 otus_write(sc, AR_GPIO_REG_DATA,
2551 otus_write(sc, AR_USB_REG_MAX_AGG_UPLOAD, (1 << 2));
2554 otus_write(sc, AR_USB_REG_UPLOAD_TIME_CTL, 0x80);
2601 otus_write(sc, AR_PHY_SWITCH_COM, tmp);
2604 otus_write(sc, AR_PHY_SWITCH_CHAIN_0, tmp);
2607 otus_write(sc, AR_PHY_SWITCH_CHAIN_0 + offset, tmp);
2613 otus_write(sc, AR_PHY_SETTLING, tmp);
2619 otus_write(sc, AR_PHY_DESIRED_SZ, tmp);
2623 otus_write(sc, AR_PHY_RF_CTL4, tmp);
2628 otus_write(sc, AR_PHY_RF_CTL3, tmp);
2633 otus_write(sc, AR_PHY_CCA, tmp);
2638 otus_write(sc, AR_PHY_RXGAIN, tmp);
2643 otus_write(sc, AR_PHY_RXGAIN + offset, tmp);
2652 otus_write(sc, AR_PHY_GAIN_2GHZ, tmp);
2657 otus_write(sc, AR_PHY_GAIN_2GHZ + offset, tmp);
2662 otus_write(sc, AR_PHY_TIMING_CTRL4, tmp);
2667 otus_write(sc, AR_PHY_TIMING_CTRL4 + offset, tmp);
2672 otus_write(sc, AR_PHY_TPCRG1, tmp);
2691 otus_write(sc, AR_PHY(ar5416_phy_regs[i]), vals[i]);
2699 otus_write(sc, AR_PHY_POWER_TX_RATE_MAX, 0x7f);
2700 otus_write(sc, AR_PHY_POWER_TX_RATE1, 0x3f3f3f3f);
2701 otus_write(sc, AR_PHY_POWER_TX_RATE2, 0x3f3f3f3f);
2702 otus_write(sc, AR_PHY_POWER_TX_RATE3, 0x3f3f3f3f);
2703 otus_write(sc, AR_PHY_POWER_TX_RATE4, 0x3f3f3f3f);
2704 otus_write
2705 otus_write(sc, AR_PHY_POWER_TX_RATE6, 0x3f3f3f3f);
2706 otus_write(sc, AR_PHY_POWER_TX_RATE7, 0x3f3f3f3f);
2707 otus_write(sc, AR_PHY_POWER_TX_RATE8, 0x3f3f3f3f);
2708 otus_write(sc, AR_PHY_POWER_TX_RATE9, 0x3f3f3f3f);
2711 otus_write(sc, 0x1d4014, 0x5163);
2713 otus_write(sc, 0x1d4014, 0x5143);
2758 otus_write(sc, AR_PHY(44), data);
2761 otus_write(sc, AR_PHY(58), data);
2814 otus_write(sc, AR_MAC_REG_DYNAMIC_SIFS_ACK, tmp);
2819 otus_write(sc, AR_PHY_HEAVY_CLIP_ENABLE, 0x200);
2833 otus_write(sc, 0x1d4004, sc->sc_bb_reset ? 0x800 : 0x400);
2837 otus_write(sc, 0x1d4004, 0);
2854 otus_write(sc, AR_PHY(ar5416_banks_regs[i]), vals[i]);
2868 otus_write(sc, AR_PHY_TURBO, tmp);
3076 otus_write(sc, AR_MAC_REG_BSSID_L,
3078 otus_write(sc, AR_MAC_REG_BSSID_H,
3091 otus_write(sc, AR_MAC_REG_MAC_ADDR_L,
3093 otus_write(sc, AR_MAC_REG_MAC_ADDR_H,
3153 otus_write(sc, AR_GPIO_REG_DATA, led_state);
3217 otus_write(sc, AR_MAC_REG_POWERMANAGEMENT, pm_mode);
3218 otus_write(sc, AR_MAC_REG_FRAMETYPE_FILTER, filter);
3219 otus_write(sc, AR_MAC_REG_SNIFFER, sniffer);
3230 otus_write(sc, AR_MAC_REG_DMA, AR_MAC_REG_DMA_ENABLE);
3272 otus_write(sc, AR_MAC_REG_DMA, AR_MAC_REG_DMA_OFF);
Indexes created Thu Oct 02 14:10:14 GMT 2025