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Lines Matching defs:urtwn_bb_read

350 #define	urtwn_bb_read	urtwn_read_4
1238 	reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0));
1240 		reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));
1256 	if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) {
1257 		val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain));
1259 		val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain));
2045 			reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
2050 				reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
2089 		reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
2094 			reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
3911 		reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO);
3915 		reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO);
3919 		reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING);
3923 		reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
3927 		reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);
3931 		reg = urtwn_bb_read(sc, 0xe74);
3934 		reg = urtwn_bb_read(sc, 0xe78);
3937 		reg = urtwn_bb_read(sc, 0xe7c);
3940 		reg = urtwn_bb_read(sc, 0xe80);
3943 		reg = urtwn_bb_read(sc, 0xe88);
3967 		reg = urtwn_bb_read(sc, R92C_AFE_CTRL3);
3977 		reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL);
3982 		if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) &
4019 		saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask;
4022 		reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
4028 		reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
4034 		reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
4038 		reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
4059 		reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask;
4210 		reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);
4214 		reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
4220 		reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);
4226 		reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
4504 		    urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ);
4506 		    urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ);
4509 		reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM);
4513 		reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF);
4518 		    urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) &
4521 		reg = urtwn_bb_read(sc, 0x818);
4533 		    urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ);
4535 		    urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ);
4540 			    urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) |
4581 	reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
4582 	reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR);
4583 	reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1));
4587 		addaBackup[i] = urtwn_bb_read(sc, addaReg[i]);
4604 	piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) &
4608 		    urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))|
4611 		    urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))|
4667 		    urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) &
4670 		    urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) &
4978 	reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);
4981 	reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);
5013 		    urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13));