Lines Matching defs:urtwn_bb_write
349 #define urtwn_bb_write urtwn_write_4
1211 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
1220 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
1229 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
1243 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
1247 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain),
1252 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
2047 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
2052 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
2091 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
2096 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
3905 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]);
3913 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg);
3917 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg);
3921 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg);
3925 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg);
3929 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg);
3933 urtwn_bb_write(sc, 0xe74, reg);
3936 urtwn_bb_write(sc, 0xe78, reg);
3939 urtwn_bb_write(sc, 0xe7c, reg);
3942 urtwn_bb_write(sc, 0xe80, reg);
3945 urtwn_bb_write(sc, 0xe88, reg);
3950 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]);
3956 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422);
3958 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420);
3968 urtwn_bb_write(sc, R92C_AFE_CTRL3,
3978 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL,
4024 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
4030 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
4036 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
4040 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
4060 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved);
4212 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);
4218 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
4224 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);
4228 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
4231 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain),
4236 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain),
4242 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain),
4247 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain),
4252 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain),
4257 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain),
4503 urtwn_bb_write(sc, R92C_FPGA0_RFMOD,
4505 urtwn_bb_write(sc, R92C_FPGA1_RFMOD,
4511 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg);
4515 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg);
4517 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
4523 urtwn_bb_write(sc, 0x818, reg);
4532 urtwn_bb_write(sc, R92C_FPGA0_RFMOD,
4534 urtwn_bb_write(sc, R92C_FPGA1_RFMOD,
4539 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
4607 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0),
4610 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1),
4621 urtwn_bb_write(sc, addaReg[i],
4632 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM);
4643 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT);
4646 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT);
4647 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING);
4648 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING);
4649 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING);
4652 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0);
4653 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2);
4654 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1);
4656 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0);
4657 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE);
4659 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE);
4666 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0),
4669 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1),
4683 urtwn_bb_write(sc, addaReg[i], addaBackup[i]);
4980 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
4983 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
5012 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0),
Indexes created Thu Oct 23 22:10:10 GMT 2025