Lines Matching defs:urtwn_read_1
264 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t);
1094 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr)
1158 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur)))
1761 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c;
1777 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0);
1781 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN);
1792 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN);
1807 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe);
1808 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON;
1812 reg = urtwn_read_1(sc, R92C_LEDCFG1) &
1817 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0;
1820 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90;
1823 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG);
1828 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70;
2006 urtwn_read_1(sc, R92C_BCN_CTRL) |
2017 urtwn_read_1(sc, R92C_BCN_CTRL) &
2068 urtwn_read_1(sc, R92C_BCN_CTRL) |
2077 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f);
2167 msr = urtwn_read_1(sc, R92C_MSR);
3132 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
3149 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL);
3155 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) &
3188 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF);
3190 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) &
3247 urtwn_read_1(sc, R92C_AFE_PLL_CTRL));
3254 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB |
3257 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc,
3309 val = urtwn_read_1(sc, 0x6) & 0x2;
3322 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB |
3325 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80);
3328 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80);
3331 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18);
3333 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1);
3335 if (!(urtwn_read_1(sc, 0x5) & 0x1))
3343 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10);
3570 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) {
3588 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN);
3590 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08);
3594 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT);
3612 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN);
4145 reg = urtwn_read_1(sc, 0x16);
4497 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ);
4499 reg = urtwn_read_1(sc, R92C_RRSR + 2);
4530 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ);
4571 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc,
4589 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE);
4590 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL);
4591 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1);
4712 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3);
4857 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) |
4911 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) |
4923 urtwn_read_1(sc, R92C_TRXDMA_CTRL) |
4926 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) &
5018 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT);
5157 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) {
5226 urtwn_read_1(sc, R92C_LDOV12D_CTRL) &
Indexes created Sun Oct 26 17:10:13 GMT 2025