Lines Matching defs:urtwn_read_4
266 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t);
350 #define urtwn_bb_read urtwn_read_4
1124 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr)
1277 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) ==
1295 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);
1302 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);
1388 reg = urtwn_read_4(sc, R92C_SYS_CFG);
1396 if (MS(urtwn_read_4(sc, R92C_HPON_FSM),
1982 urtwn_read_4(sc, R92C_RCR) |
2060 urtwn_read_4(sc, R92C_RCR) &
2104 urtwn_read_4(sc, R92C_RCR) &
2134 urtwn_read_4(sc, R92C_RCR) &
2139 urtwn_read_4(sc, R92C_RCR) |
2173 urtwn_read_4(sc, R92C_RCR) |
2186 urtwn_read_4(sc, R92C_RCR) &
2190 reg = urtwn_read_4(sc, R92C_TCR);
3235 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){
3269 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc,
3381 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN;
3384 val = urtwn_read_4(sc, R92E_AUTO_LLT);
3484 reg = urtwn_read_4(sc, R92C_MCUFWDL);
3617 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT)
3629 reg = urtwn_read_4(sc, R92C_MCUFWDL);
3636 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY)
4576 odfm0_agccore_regs[i] = urtwn_read_4(sc,
4592 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG);
4595 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A);
4596 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B);
4598 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0));
4600 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i));
4601 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING);
4872 reg = urtwn_read_4(sc, R92C_CR);
4886 reg = urtwn_read_4(sc, R92C_RRSR);
4918 reg = urtwn_read_4(sc, R92C_TDECTRL);
5194 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00;
Indexes created Wed Oct 22 13:09:56 GMT 2025