Lines Matching defs:udl_reg_write_2
250 udl_reg_write_2(struct udl_softc *sc, uint8_t reg, uint16_t val)
1759 udl_reg_write_2(sc, UDL_REG_XDISPLAYSTART, udl_lfsr(val));
1761 udl_reg_write_2(sc, UDL_REG_XDISPLAYEND, udl_lfsr(val));
1763 udl_reg_write_2(sc, UDL_REG_YDISPLAYSTART, udl_lfsr(val));
1765 udl_reg_write_2(sc, UDL_REG_YDISPLAYEND, udl_lfsr(val));
1767 udl_reg_write_2(sc, UDL_REG_XENDCOUNT, udl_lfsr(val));
1770 udl_reg_write_2(sc, UDL_REG_HSYNCSTART, udl_lfsr(1));
1771 udl_reg_write_2(sc, UDL_REG_HSYNCEND, udl_lfsr(val));
1773 udl_reg_write_2(sc, UDL_REG_HSYNCSTART, udl_lfsr(val));
1774 udl_reg_write_2(sc, UDL_REG_HSYNCEND, udl_lfsr(1));
1777 udl_reg_write_2(sc, UDL_REG_HPIXELS, val);
1779 udl_reg_write_2(sc, UDL_REG_YENDCOUNT, udl_lfsr(val));
1782 udl_reg_write_2(sc, UDL_REG_VSYNCSTART, udl_lfsr(0));
1783 udl_reg_write_2(sc, UDL_REG_VSYNCEND, udl_lfsr(val));
1785 udl_reg_write_2(sc, UDL_REG_VSYNCSTART, udl_lfsr(val));
1786 udl_reg_write_2(sc, UDL_REG_VSYNCEND, udl_lfsr(0));
1789 udl_reg_write_2(sc, UDL_REG_VPIXELS, val);
1791 udl_reg_write_2(sc, UDL_REG_PIXELCLOCK5KHZ, bswap16(val));