Cross Reference: /src/sys/dev/usb/xhci.c

Lines Matching defs:dci
501     const u_int dci)
503 	return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci);
509     const u_int dci)
511 	return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci);
578     u_int dci)
583 	cp = xhci_slot_get_dcv(sc, xs, dci);
711 	size_t i, j, bn, dci;
760 		for (dci = XHCI_DCI_SLOT; dci <= XHCI_MAX_DCI; dci++) {
763 			if (xhci_get_epstate(sc, xs, dci) !=
769 			err = xhci_stop_endpoint_cmd(sc, xs, dci,
774 				    " slot %zu dci %zu err %d\n",
775 				    i, dci, err);
937 	size_t i, j, bn, dci;
1115 		for (dci = XHCI_DCI_SLOT; dci <= XHCI_MAX_DCI; dci++) {
1117 dci) !=
1122 			xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci);
1893 	const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
1899 	XHCIHIST_CALLARGS("slot %ju dci %ju epaddr 0x%02jx attr 0x%02jx",
1900 	    xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress,
1913 	    xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1);
1923 	HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, dci),
1950 	const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
1954 	XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0);
1961 	    XHCI_TRB_3_EP_SET(dci) |
1976 xhci_stop_endpoint_cmd(struct xhci_softc *sc, struct xhci_slot *xs, u_int dci,
1983 	XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0);
1990 	    XHCI_TRB_3_EP_SET(dci) |
2004 	const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
2007 	XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0);
2011 	return xhci_stop_endpoint_cmd(sc, xs, dci, 0);
2027 	const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
2028 	struct xhci_ring * const xr = xs->xs_xr[dci];
2032 	XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0);
2043 	    XHCI_TRB_3_EP_SET(dci) |
2065 	const u_int dci = xhci_ep_get_dci(ed);
2072 	DPRINTFN(1, " dci %ju type 0x%02jx epaddr 0x%02jx attr 0x%02jx",
2123 	KASSERT(xs->xs_xr[dci] == NULL);
2126 	err = xhci_ring_init(sc, &xs->xs_xr[dci], XHCI_TRANSFER_RING_TRBS,
2152 	const u_int dci = xhci_ep_get_dci(ed);
2168 	XHCIHIST_CALLARGS("pipe %#jx slot %ju dci %ju",
2169 	    (uintptr_t)pipe, xs->xs_idx, dci, 0);
2177 	if (dci == XHCI_DCI_EP_CONTROL) {
2184 	if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED)
2193 	cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci));
2196 	/* XXX should be most significant one, not dci? */
2198 	cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci));
2201 	xhci_host_dequeue(xs->xs_xr[dci]);
2214 	xhci_ring_free(sc, &xs->xs_xr[dci]);
2215 	xs->xs_xr[dci] = NULL;
2265 	const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
2268 	XHCIHIST_CALLARGS("pipe %#jx slot %ju dci %ju",
2269 	    (uintptr_t)pipe, xs->xs_idx, dci, 0);
2281 	switch (xhci_get_epstate(sc, xs, dci)) {
2292 	switch (xhci_get_epstate(sc, xs, dci)) {
2315 	const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
2316 	struct xhci_ring * const tr = xs->xs_xr[dci];
2365 	const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
2366 	struct xhci_ring * const tr = xs->xs_xr[dci];
2421 	u_int slot, dci;
2435 	dci = XHCI_TRB_3_EP_GET(trb_3);
2437 	xr = xs->xs_xr[dci];
2460 			DPRINTFN(1, "Ignore #%ju: cookie %#jx cc %ju dci %ju",
2461 			    idx, (uintptr_t)xx, trbcode, dci);
2553 		DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0);
2558 		DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0);
3541 	u_int dci;
3547 	for (dci = XHCI_DCI_SLOT; dci <= XHCI_MAX_DCI; dci++) {
3548 		if (xs->xs_xr[dci] != NULL)
3549 			xhci_ring_free(sc, &xs->xs_xr[dci]);
3599 	const u_int dci = xhci_ep_get_dci(ed);
3605 	XHCIHIST_CALLARGS("pipe %#jx: slot %ju dci %ju speed %ju",
3606 	    (uintptr_t)pipe, xs->xs_idx, dci, speed);
3611 	cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci));
3618 	    XHCI_SCTX_0_CTX_NUM_SET(dci) |
3632 	cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci));
3649 	DPRINTFN(4, "setting on dci %ju ival %ju mult %ju mps %#jx",
3650 	    dci, XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_0_MULT_GET(cp[0]),
3661 	    xhci_ring_trbp(xs->xs_xr[dci], 0) |
3669 	struct xhci_ring *xr = xs->xs_xr[dci];
4460 	const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
4461 	struct xhci_ring * const tr = xs->xs_xr[dci];
4530 	xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci);
4591 	const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
4592 	struct xhci_ring * const tr = xs->xs_xr[dci];
4607 	XHCIHIST_CALLARGS("%#jx slot %ju dci %ju",
4608 	    (uintptr_t)xfer, xs->xs_idx, dci, 0);
4689 	xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci);
4717 	const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
4722 	XHCIHIST_CALLARGS("%#jx slot %ju dci %ju",
4723 	    (uintptr_t)xfer, xs->xs_idx, dci, 0);
4746 	const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
4747 	struct xhci_ring * const tr = xs->xs_xr[dci];
4758 	XHCIHIST_CALLARGS("%#jx slot %ju dci %ju",
4759 	    (uintptr_t)xfer, xs->xs_idx, dci, 0);
4810 	xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci);
4831 	const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
4836 	XHCIHIST_CALLARGS("%#jx slot %ju dci %ju",
4837 	    (uintptr_t)xfer, xs->xs_idx, dci, 0);
4876 	const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
4877 	struct xhci_ring * const tr = xs->xs_xr[dci];
4888 	XHCIHIST_CALLARGS("%#jx slot %ju dci %ju",
4889 	    (uintptr_t)xfer, xs->xs_idx, dci, 0);
4921 	xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci);
4943 	const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
4948 	XHCIHIST_CALLARGS("%#jx slot %ju dci %ju",
4949 	    (uintptr_t)xfer, xs->xs_idx, dci, 0);
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