Lines Matching defs:trb
552 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status,
555 trb->trb_0 = htole64(parameter);
556 trb->trb_2 = htole32(status);
557 trb->trb_3 = htole32(control);
1885 * Construct input contexts and issue TRB to open pipe.
1895 struct xhci_soft_trb trb;
1915 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0);
1916 trb.trb_2 = 0;
1917 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1920 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);
1951 struct xhci_soft_trb trb;
1958 trb.trb_0 = 0;
1959 trb.trb_2 = 0;
1960 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1964 if (xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT)) {
1979 struct xhci_soft_trb trb;
1987 trb.trb_0 = 0;
1988 trb.trb_2 = 0;
1989 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1994 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
2029 struct xhci_soft_trb trb;
2040 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */
2041 trb.trb_2 = 0;
2042 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
2046 if (xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT)) {
2153 struct xhci_soft_trb trb;
2206 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0);
2207 trb.trb_2 = 0;
2208 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
2211 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
2416 const struct xhci_trb * const trb)
2430 trb_0 = le64toh(trb->trb_0);
2431 trb_2 = le32toh(trb->trb_2);
2432 trb_3 = le32toh(trb->trb_3);
2452 /* clear cookie of consumed TRB */
2462 DPRINTFN(1, " orig TRB %#jx type %ju", trb_0,
2497 /* 4.11.5.2 Event Data TRB */
2522 * + by checking the type of original TRB if ED==0.
2611 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb)
2620 trb_0 = le64toh(trb->trb_0);
2621 trb_2 = le32toh(trb->trb_2);
2622 trb_3 = le32toh(trb->trb_3);
2639 "0x%08jx 0x%08jx", (uintptr_t)trb, trb_0, trb_2, trb_3);
2649 const struct xhci_trb * const trb)
2656 trb_0 = le64toh(trb->trb_0);
2657 trb_2 = le32toh(trb->trb_2);
2658 trb_3 = le32toh(trb->trb_3);
2661 (uintptr_t)trb, trb_0, trb_2, trb_3);
2665 * TRB Pointer is invalid for these completion codes.
2681 xhci_event_transfer(sc, trb);
2684 xhci_event_cmd(sc, trb);
2700 struct xhci_trb *trb;
2729 trb = &er->xr_trb[i];
2730 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
2735 xhci_handle_event(sc, trb);
3149 * that a LINK trb is only allowed at the end of a burst of
3151 * Arbitrary aligned LINK trb definitely fail on Ivy bridge.
3152 * The simple solution is not to allow a LINK trb in the middle
3155 * ASMedia) that seem to lock up if they process a LINK trb but
3156 * cannot process the linked-to trb yet.
3157 * The code should write the 'cycle' bit on the link trb AFTER
3158 * adding the other trb.
3188 * If this is a first TRB, mark it invalid to prevent
3209 /* Now invert cycle bit of first TRB */
3282 struct xhci_soft_trb * const trb, int timeout)
3289 trb->trb_0, trb->trb_2, trb->trb_3, 0);
3301 * If enqueue pointer points at last of ring, it's Link TRB,
3302 * command TRB will be stored in 0th TRB.
3312 xhci_ring_put(sc, cr, NULL, trb, 1);
3326 trb->trb_0 = sc->sc_result_trb.trb_0;
3327 trb->trb_2 = sc->sc_result_trb.trb_2;
3328 trb->trb_3 = sc->sc_result_trb.trb_3;
3331 trb->trb_0, trb->trb_2, trb->trb_3, 0);
3333 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) {
3340 XHCI_TRB_2_ERROR_GET(trb->trb_2), 0, 0, 0);
3357 xhci_do_command(struct xhci_softc * const sc, struct xhci_soft_trb * const trb,
3362 usbd_status ret = xhci_do_command_locked(sc, trb, timeout);
3371 struct xhci_soft_trb trb;
3376 trb.trb_0 = 0;
3377 trb.trb_2 = 0;
3378 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT);
3380 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);
3385 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3);
3399 struct xhci_soft_trb trb;
3408 trb.trb_0 = 0;
3409 trb.trb_2 = 0;
3410 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot) |
3413 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
3438 struct xhci_soft_trb trb;
3450 trb.trb_0 = icp;
3451 trb.trb_2 = 0;
3452 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) |
3456 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);
3458 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS)
3468 struct xhci_soft_trb trb;
3488 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0);
3489 trb.trb_2 = 0;
3490 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
3493 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);
3513 * TRB DMA buffer for each endpoint.
4796 * (or more) TRB should be used.
4797 * If multiple TRB are used the td_size field must be set correctly.
4800 * Setting it to 1 in the last TRB
Indexes created Sat Oct 11 08:10:02 GMT 2025