Cross Reference: /src/sys/dev/vme/si.c

Lines Matching refs:csr
364 	uint16_t csr;
370 	csr = SIREG_READ(ncr_sc, SIREG_CSR);
372 	NCR_TRACE("si_intr: csr=0x%x\n", csr);
374 	if (csr & SI_CSR_DMA_CONFLICT) {
378 	if (csr & SI_CSR_DMA_BUS_ERR) {
386 		csr |= SI_CSR_DMA_IP;
389 	if (csr & (SI_CSR_SBC_IP | SI_CSR_DMA_IP)) {
420 	 * The reset bits in the CSR are active low.
561 	int tmo, csr_mask, csr;
572 		csr = SIREG_READ(ncr_sc, SIREG_CSR);
573 		if (csr & csr_mask)
587 		printf("%s: done, csr=0x%x\n", __func__, csr);
608 	uint16_t csr;
617 	csr = SIREG_READ(ncr_sc, SIREG_CSR);
618 	csr &= ~SI_CSR_SEND;
619 	csr |= SI_CSR_DMA_EN;
620 	SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
630 	uint16_t csr;
632 	csr = SIREG_READ(ncr_sc, SIREG_CSR);
633 	csr &= ~SI_CSR_DMA_EN;
634 	SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
655 	uint16_t csr;
664 	csr = SIREG_READ(ncr_sc, SIREG_CSR);
667 	csr &= ~SI_CSR_DMA_EN;
670 	csr &= ~SI_CSR_FIFO_RES;		/* active low */
671 	SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
672 	csr |= SI_CSR_FIFO_RES;
673 	SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
693 		csr |= SI_CSR_SEND;
695 		csr &= ~SI_CSR_SEND;
700 		csr |= SI_CSR_BPCON;
702 		csr &= ~SI_CSR_BPCON;
705 	SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
729 	uint16_t csr;
768 	csr = SIREG_READ(ncr_sc, SIREG_CSR);
769 	csr |= SI_CSR_DMA_EN;
770 	SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
796 	uint16_t csr;
808 	csr = SIREG_READ(ncr_sc, SIREG_CSR);
811 	csr &= ~SI_CSR_DMA_EN;
812 	SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
814 	if (csr & (SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR)) {
815 		printf("si: DMA error, csr=0x%x, reset\n", csr);
870 		((csr & SI_CSR_LOB) != 0)) {
878 		printf("si: got left-over bytes: bprh=%x, bprl=%x, csr=%x\n",
879 			bprh, bprl, csr);
882 		if (csr & SI_CSR_BPCON) {
886 			switch (csr & SI_CSR_LOB) {
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