Lines Matching refs:And
5 * Redistribution and use in source and binary forms, with or without modification,
9 * this list of conditions and the following disclaimer.
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
92 grammar.asl 6800: And (Local0, 1, Local0) // Local0 &= 1
118 /* Device with _STA and _INI */
153 /* Device with _STA and _INI, but not present */
574 If(LEqual(And(LANS,0x30),0x30)){
832 If(And(Arg1,0x80)) {
1706 Store ("++++++++ And (0xF0F0F0F0, 0x11111111, Local2)", Debug)
1707 And (0xF0F0F0F0, 0x11111111, Local2)
2003 // test for IfOp and ElseOp, including validation of object stack cleanup
2011 // and no Else branch
2021 // NINR control method does not execute If branch and has no Else branch
2174 // Test If (And ()) with no save of And result
2175 If (And (3, 1, ))
2184 // Test If (And ()) with no save of And result
2185 If (And (4, 1, ))
2752 // This is required to support _PSR on IBM ThinkPad 560D and
3084 //This code tests the bitwise AndOp and OrOp Operator terms
3087 //And - Bitwise And
3088 //AndTerm := And(
3093 //Source1 and Source2 are evaluated as integer data types,
3094 // a bit-wise AND is performed, and the result is optionally
3105 //Source1 and Source2 are evaluated as integer data types,
3106 // a bit-wide OR is performed, and the result is optionally
3118 //Create System Memory Operation Region and field overlays
3128 //And with Byte Data
3133 //And with Word Data
3138 //And with DWord Data
3145 //Check with 1 And 1 on byte data
3146 And(BYT1, BYT2, BRSL)
3150 //Check with 1 And 1 on Word data
3151 And(WRD1, WRD2, WRSL)
3157 //Check with 1 And 1 Dword
3158 And(DWD1, DWD2, DRSL)
3164 //Check with 0 And 0 on byte data
3168 And(BYT1, BYT2, BRSL)
3174 //Check with 0 And 0 on Word data
3178 And(WRD1, WRD2, WRSL)
3184 //Check with 0 And 0 Dword
3188 And(DWD1, DWD2, DRSL)
3195 //Check with 1 And 0 on byte data
3199 And(BYT1, BYT2, BRSL)
3205 //Check with 1 And 0 on Word data
3209 And(WRD1, WRD2, WRSL)
3215 //Check with 1 And 0 on Dword
3219 And(DWD1, DWD2, DRSL)
3380 // Used for debugging, the Breakpoint opcode stops the execution and enters the AML debugger.
3422 // create System Memory Operation Region and field overlays
3515 // create System Memory Operation Region and field overlays
3608 // Success will return 0 and failure will return a non zero number. Check the source code for
3613 //Create System Memory Operation Region and field overlays
3622 //And with Byte Data
3627 //And with Word Data
3632 //And with DWord Data
3639 Method (ANDL,2) // Test Logical And
3817 //This method tests LGreater and LNot operator
3938 // Source is evaluated as integer data type, and the one-based bit location of
3941 // first bit, 2 means the left-most bit set is the second bit, and so on.
3948 // Source is evaluated as integer data type, and the one-based bit location of
3951 // 32nd bit, 31 means the first bit set is the 31st bit, and so on.
3959 // Create System Memory Operation Region and field overlays
3983 // Arg0 is the actual data and Arg1 is the bit position
4122 // create System Memory Operation Region and field overlays
4232 //Source1 and Source2 are evaluated as integer data types, a bit-wise NAND is performed, and the result is optionally
4241 //Source1 andand the result is optionally
4248 //Source1 is evaluated as an integer data type, a bit-wise NOT is performed, and the result is optionally stored in
4256 //Create System Memory Operation Region and field overlays
4266 //And with Byte Data
4271 //And with Word Data
4276 //And with DWord Data
4477 //Source and ShiftCount are evaluated as integer data types. Source is shifted right with the most significant bit
4485 //Source and ShiftCount are evaluated as integer data types. Source is shifted left with the least significant
4492 //Create System Memory Operation Region and field overlays
4504 //And with Byte Data
4508 //And with Word Data
4512 //And with DWord Data
4537 //Local0->8 and Local1->2
4585 //And with Byte Data
4589 //And with Word Data
4593 //And with DWord Data
4613 //Local0->8 and Local1->2
4674 // test Xor.asl and slightly modified
4683 //"Source1" and "Source2" are evaluated as integers, a bit-wise XOR is performed, and the result is optionally stored in
4687 //This Method tests XOr operator for all the data types i.e. BYTE, WORD and DWORD
4740 // (BYT1) Bit1 ->0 and (BYT2)Bit2 -> 0 condition
4748 // (BYT1) Bit1 ->1 and (BYT2)Bit2 -> 1 condition
4756 // (BYT1) Bit1 ->1 and (BYT)Bit2 -> 0 condition
4764 //(BYT1) Bit1 ->0 and (BYT2)Bit2 -> 1 condition
4802 // (WRD1) Bit1 ->0 and (WRD2)Bit2 -> 0 condition
4809 // (WRD1) Bit1 ->1 and (WRD2)Bit2 -> 1 condition
4816 // (WRD1) Bit1 ->1 and (WRD2)Bit2 -> 0 condition
4823 //(WRD1) Bit1 ->0 and (WRD2)Bit2 -> 1 condition
4857 // (DWD1) Bit1 ->0 and (DWD2)Bit2 -> 0 condition
4864 // (DWD1) Bit1 ->1 and (DWD2)Bit2 -> 1 condition
4871 // (DWD1) Bit1 ->1 and (DWD2)Bit2 -> 0 condition
4878 //(DWD1) Bit1 ->0 and (DWD2)Bit2 -> 1 condition
4885 // (DWD1) Bit1 ->1 and (DWD2)Bit2 -> 0 condition
5020 // Tests need to be added for Arg0 and Name buffers.
5105 // WORD, and DWORD field element accesses. Validation is performed
5106 // using both misaligned field entries and aligned field entries.
5637 // EventOp, ResetOp, SignalOp, and WaitOp test cases.
5645 { // TEVN control method to test ResetOp, SignalOp, and WaitOp
5791 } // TEVN control method to test ResetOp, SignalOp, and WaitOp
5813 // final package, PKG2, has 4 elements and the SizeOf operator is expected
5843 // exercise the SizeOf operator. STR0 and STR1 are expected to be equal,
5844 // STR2 is expected to have a different SizeOf value than STR0 and STR1.
5850 Name (STR2, "Needless to say, Mike and ACPI are frequently at odds")
5853 // between strings and packages or buffers
5921 // In this case, both Local0 and Local1 should have the same Size
5930 // Now create a case where Local0 and Local1 are different
5982 And (Local0, 16, Local0)
6016 And (Local0, 0xFFFEFFFE, Local0)
6277 { // This control method will take two bytes and make them into a WORD
6296 // by 100. We expect to get 74 for the remainder and 1 for
6353 { // TST_: provides a different namespace scope for IFE0 and IFE1
6365 } // TST_: provides a different namespace scope for IFE0 and IFE1
6401 // and performing an IndexOp on the resulting buffer.
6423 // validate BUF0 and BUF1 are still buffers
6500 // create EC's region and field
6729 // BIT0 and BIT2 should be clear
6752 // be set. BIT4, BIT6. BIT5 and BIT7 should be clear.
6799 // an IndexOp target and validating that changing source and destination
6817 And (Local0, 1, Local0) // Local0 &= 1
6848 0, // Power Unit (0 ==> mWh and mW)
6863 And (Arg0, 7, Local0) // Local0 = Arg0 & 7
6869 // verify source and destination packages can be altered independent
7734 // MatchOp, DerefOfOp, and IndexOp of nested packages.
7807 And (Match (DerefOf (Index (TIM0, 0, )), MGE, PIO0, MTR, 0, 0), 3, Local0)
7820 Store ("And(Match(DerefOf(Index(TIM0,0)),... PASS", Debug)
7916 // This code tests the Break term and While term
8040 Increment (CNT0) // check if Break exited both If and While
8070 // shifting of Field elements and reading Field elements greater than 64 bits.
8318 // verify object type and value returned by DerefOf(Index(Buffer,Element,))
8453 Store ("SRCB and DEST independent PASS", Debug)
8509 // verify Local0 and Local1 are Buffers
8587 Store ("Mem and Pkg independent PASS", Debug)
8611 // validate source and destination buffers are independent of each
8614 // Buffer) and FB2P (store from Field Buffer into Index'ed Package)
8672 // buffer, package, and string package elements
9026 // TBD: strings and packages
9329 If (And (Local0, 0x01))
9332 If (And (Local0, 0x02))
9335 If (And (Local0, 0x04))
9338 If (And (Local0, 0x08))
Indexes created Fri Oct 17 22:10:11 GMT 2025