Lines Matching defs:UCHAR
50 #ifndef UCHAR
51 typedef unsigned char UCHAR;
213 UCHAR ucTableFormatRevision; //Change it when the Parser is not backward compatible
214 UCHAR ucTableContentRevision; //Change it only when the table needs to change but the firmware
224 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
239 UCHAR ucExtendedFunctionCode;
240 UCHAR ucReserved;
247 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
262 UCHAR ucExtendedFunctionCode;
263 UCHAR ucReserved;
443 UCHAR ucAction; //0:reserved //1:Memory //2:Engine
444 UCHAR ucReserved; //may expand to return larger Fbdiv later
445 UCHAR ucFbDiv; //return value
446 UCHAR ucPostDiv; //return value
452 UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
454 UCHAR ucPostDiv; //return post div to be written to register
502 UCHAR ucRefDiv; //Output Parameter
503 UCHAR ucPostDiv; //Output Parameter
504 UCHAR ucCntlFlag; //Output Parameter
505 UCHAR ucReserved;
535 UCHAR ucRefDiv; //Output Parameter
536 UCHAR ucPostDiv; //Output Parameter
539 UCHAR ucCntlFlag; //Output Flags
540 UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode
542 UCHAR ucReserved;
562 UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider
563 UCHAR ucPllPostDiv; //Output Parameter: PLL post divider
564 UCHAR ucPllCntlFlag; //Output Flags: control flag
565 UCHAR ucReserved;
587 UCHAR ucSclkPostDiv; //PLL post divider = 2^ucSclkPostDiv
588 UCHAR ucSclkVcoMode; //0: 4G~8Ghz, 1:3G~6Ghz,3: 2G~4Ghz, 2:Reserved
589 UCHAR ucSclkPllRange; //GreenTable SCLK PLL range entry index ( 0~7 )
590 UCHAR ucSscEnable;
610 UCHAR ucDllSpeed; //Output
611 UCHAR ucPostDiv; //Output
613 UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
614 UCHAR ucPllCntlFlag; //Output:
616 UCHAR ucBWCntl;
666 UCHAR ucMclkDPMState;
667 UCHAR ucReserved[3];
757 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
758 UCHAR ucPadding[3];
767 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ...
768 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
769 UCHAR ucPadding[2];
774 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ...
775 UCHAR ucEnable; // ATOM_ENABLE/ATOM_DISABLE/ATOM_INIT
776 UCHAR ucPadding[2];
785 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
786 UCHAR ucPadding[3];
796 UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
797 UCHAR ucMisc; //Valid only when table revision =1.3 and above
815 UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
816 UCHAR ucAction; // 0: turn off encoder
831 UCHAR ucConfig;
839 UCHAR ucAction; // =0: turn off encoder
841 UCHAR ucEncoderMode;
847 UCHAR ucLaneNum; // how many lanes to enable
848 UCHAR ucReserved[2];
891 UCHAR ucReserved1:2;
892 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
893 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
894 UCHAR ucReserved:1;
895 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
897 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
898 UCHAR ucReserved:1;
899 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
900 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
901 UCHAR ucReserved1:2;
910 UCHAR ucAction;
911 UCHAR ucEncoderMode;
917 UCHAR ucLaneNum; // how many lanes to enable
918 UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS
919 UCHAR ucReserved;
964 UCHAR ucReserved1:1;
965 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
966 UCHAR ucReserved:3;
967 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
969 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
970 UCHAR ucReserved:3;
971 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
972 UCHAR ucReserved1:1;
991 UCHAR ucAction;
993 UCHAR
1000 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
1005 UCHAR ucLaneNum; // how many lanes to enable
1006 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
1007 UCHAR ucReserved;
1017 UCHAR ucReserved1:1;
1018 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
1019 UCHAR ucReserved:2;
1020 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
1022 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
1023 UCHAR ucReserved:2;
1024 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
1025 UCHAR ucReserved1:1;
1048 UCHAR ucConfig;
1050 UCHAR ucAction;
1052 UCHAR ucEncoderMode;
1059 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
1064 UCHAR ucLaneNum; // how many lanes to enable
1065 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
1066 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version
1085 UCHAR ucDigId; // 0~6 map to DIG0~DIG6
1086 UCHAR ucAction; // = ATOM_ENOCODER_CMD_STREAM_SETUP
1087 UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
1088 UCHAR ucLaneNum; // Lane number
1090 UCHAR ucBitPerColor;
1091 UCHAR ucLinkRateIn270Mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc
1092 UCHAR ucReserved[2];
1097 UCHAR ucDigId; // 0~6 map to DIG0~DIG6
1098 UCHAR ucAction; // = ATOM_ENOCODER_CMD_LINK_SETUP
1099 UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
1100 UCHAR ucLaneNum; // Lane number
1102 UCHAR ucHPDSel;
1103 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
1104 UCHAR ucReserved[2];
1109 UCHAR ucDigId; // 0~6 map to DIG0~DIG6
1110 UCHAR ucAction; // = ATOM_ENCODER_CMD_DPLINK_SETUP
1111 UCHAR ucPanelMode; // =0: external DP
1114 UCHAR ucReserved;
1120 UCHAR ucDigId; // 0~6 map to DIG0~DIG6
1121 UCHAR ucAction; // = rest of generic encoder command which does not carry any parameters
1122 UCHAR ucReserved[2];
1152 UCHAR ucLaneSel;
1153 UCHAR ucLaneSet;
1164 UCHAR ucConfig;
1178 UCHAR ucAction; // =0: turn off encoder
1180 UCHAR ucReserved[4];
1233 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1236 UCHAR ucReserved:1;
1237 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1238 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
1239 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1242 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1243 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1245 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1246 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1247 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1249 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
1250 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1251 UCHAR ucReserved:1;
1252 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1293 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1294 UCHAR ucReserved[4];
1300 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1303 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1304 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1305 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1307 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1308 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1310 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1311 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1312 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1314 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1315 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1316 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1332 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1333 UCHAR ucLaneNum;
1334 UCHAR ucReserved[3];
1375 UCHAR ucLaneSel;
1378 UCHAR ucLaneSet;
1381 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1382 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1383 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1385 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1386 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1387 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1396 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1399 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1400 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1401 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1403 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1404 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1406 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1407 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1408 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1410 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1411 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1412 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1429 UCHAR ucConfig;
1431 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1432 UCHAR ucLaneNum;
1433 UCHAR ucReserved[3];
1465 UCHAR ucReservd1:1;
1466 UCHAR ucHPDSel:3;
1467 UCHAR ucPhyClkSrcId:2;
1468 UCHAR ucCoherentMode:1;
1469 UCHAR ucReserved:1;
1471 UCHAR ucReserved:1;
1472 UCHAR ucCoherentMode:1;
1473 UCHAR ucPhyClkSrcId:2;
1474 UCHAR ucHPDSel:3;
1475 UCHAR ucReservd1:1;
1482 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
1483 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx
1484 UCHAR ucLaneNum; // indicate lane number 1-8
1485 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h
1486 UCHAR ucDigMode; // indicate DIG mode
1489 UCHAR ucConfig;
1491 UCHAR ucDigEncoderSel; // indicate DIG front end encoder
1492 UCHAR ucDPLaneSet;
1493 UCHAR ucReserved;
1494 UCHAR ucReserved1;
1563 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
1564 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx
1567 UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
1568 UCHAR ucDPLaneSet; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"
1570 UCHAR ucLaneNum; // Lane number
1572 UCHAR ucHPDSel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
1573 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
1574 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h
1575 UCHAR ucReserved;
1618 UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
1619 UCHAR ucAction; //
1620 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
1621 UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
1622 UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
1623 UCHAR ucReserved;
1661 UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE
1666 UCHAR aucPadding[3]; // padding to DWORD aligned
1706 UCHAR ucAction;
1707 UCHAR ucBriLevel;
1718 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1719 UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF
1733 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1734 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1735 UCHAR ucPadding[2];
1748 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1749 UCHAR ucPadding[3];
1758 UCHAR ucH_Replication; // horizontal replication
1759 UCHAR ucV_Replication; // vertical replication
1760 UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1761 UCHAR ucPadding;
1770 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1771 UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
1772 UCHAR ucPadding[2];
1778 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1779 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
1780 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
1781 UCHAR ucPadding;
1807 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1808 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
1809 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
1810 UCHAR ucDstBpc; // PANEL_6/8/10/12BIT_PER_COLOR
1825 UCHAR ucPostDiv; // post divider
1826 UCHAR ucFracFbDiv; // fractional feedback divider
1827 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1828 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
1829 UCHAR ucCRTC; // Which CRTC uses this Ppll
1830 UCHAR ucPadding;
1845 UCHAR ucPostDiv; // post divider
1846 UCHAR ucFracFbDiv; // fractional feedback divider
1847 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1848 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
1849 UCHAR ucCRTC; // Which CRTC uses this Ppll
1850 UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog
1892 UCHAR ucPostDiv; // post divider
1893 UCHAR ucFracFbDiv; // fractional feedback divider
1894 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1895 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h
1898 UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
1899 UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit
1901 UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
1912 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to
1915 UCHAR ucReserved;
1916 UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed.
1921 UCHAR ucPostDiv; // post divider.
1922 UCHAR ucRefDiv; // Reference divider
1923 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1924 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
1926 UCHAR ucEncoderMode; // Encoder mode:
1927 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1969 UCHAR ucPostDiv; // post divider.
1970 UCHAR ucRefDiv; // Reference divider
1971 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1972 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
1974 UCHAR ucEncoderMode; // Encoder mode:
1975 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
2007 UCHAR ucStatus;
2008 UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock
2009 UCHAR ucReserved[2];
2021 UCHAR ucPpll; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
2022 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
2024 UCHAR ucEncoderMode; // Encoder mode:
2025 UCHAR ucMiscInfo; // bit[0]= Force program PLL for pixclk
2031 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to
2032 UCHAR ucDeepColorRatio; // HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:36bpp
2033 UCHAR ucReserved[2];
2057 UCHAR ucFlag; // bit0=1: DPREFCLK bypass DFS bit0=0: DPREFCLK not bypass DFS
2058 UCHAR ucCrtc; // use when enable DCCG pixel clock ucFlag[1]=1
2059 UCHAR ucPpllId; // use when enable DCCG pixel clock ucFlag[1]=1
2060 UCHAR ucDeepColorRatio; // use when enable DCCG pixel clock ucFlag[1]=1
2079 UCHAR ucDCEClkType; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
2080 UCHAR ucDCEClkSrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx
2081 UCHAR ucDCEClkFlag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )
2082 UCHAR ucCRTC; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK
2119 UCHAR ucTransmitterID;
2120 UCHAR ucEncodeMode;
2123 UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit
2124 UCHAR ucConfig; //if none DVO, not defined yet
2126 UCHAR ucReserved[3];
2135 UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h
2136 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI
2137 UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX
2138 UCHAR ucExtTransmitterID; // external encoder id.
2139 UCHAR ucReserved[2];
2158 UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given )
2159 UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
2160 UCHAR ucReserved[2];
2177 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
2178 UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format
2179 UCHAR ucPadding[2];
2212 UCHAR ucSlaveAddr; //Read from which slave
2213 UCHAR ucLineNumber; //Read from which HW assisted line
2234 UCHAR ucData; //PS data1
2235 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2
2236 UCHAR ucSlaveAddr; //Write to which slave
2237 UCHAR ucLineNumber; //Write from which HW assisted line
2245 UCHAR ucSlaveAddr; //Write to which slave
2246 UCHAR ucLineNumber; //Write from which HW assisted line
2258 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
2259 UCHAR ucPwrBehaviorId;
2265 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
2266 UCHAR ucReserved;
2280 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
2281 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
2282 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
2283 UCHAR ucPadding[3];
2290 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
2291 UCHAR ucSpreadSpectrumStep; //
2292 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
2293 UCHAR ucSpreadSpectrumDelay;
2294 UCHAR ucSpreadSpectrumRange;
2295 UCHAR ucPadding;
2302 UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
2303 UCHAR ucSpreadSpectrumStep; //
2304 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
2305 UCHAR ucSpreadSpectrumDelay;
2306 UCHAR ucSpreadSpectrumRange;
2307 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2
2313 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2317 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
2338 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2342 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
2405 UCHAR ucMisc; // bit0=0: Enable single link
2409 UCHAR ucAction; // 0: turn off encoder
2425 UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below
2426 UCHAR ucAction; // 0: turn off encoder
2428 UCHAR ucTruncate; // bit0=0: Disable truncate
2432 UCHAR ucSpatial; // bit0=0: Disable spatial dithering
2436 UCHAR ucTemporal; // bit0=0: Disable temporal dithering
2442 UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E
2475 UCHAR ucEnable; // Enable or Disable External TMDS encoder
2476 UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
2477 UCHAR ucPadding[2];
2515 UCHAR ucDVOConfig;
2516 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
2517 UCHAR ucReseved[4];
2524 UCHAR ucDVOConfig;
2525 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
2526 UCHAR ucBitPerColor; //please refer to definition of PANEL_xBIT_PER_COLOR
2527 UCHAR ucReseved[3];
2600 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2601 UCHAR ucVoltageMode; // To set all, to set source A or source B or ...
2602 UCHAR ucVoltageIndex; // An index to tell which voltage level
2603 UCHAR ucReserved;
2608 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2609 UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode
2616 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2617 UCHAR ucVoltageMode; // Indicate action: Set voltage level
2672 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2673 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
2711 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2712 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
2733 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2734 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
2768 UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..."
2769 UCHAR ucAction; // 0: turn off encoder
2845 UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
2846 UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
2847 UCHAR ucVideoPortInfo; // Provides the video port capabilities
2848 UCHAR ucHostPortInfo; // Provides host port configuration information
2859 UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
2860 UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
2861 UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting
2862 UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
2863 UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
2864 UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
2865 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3)
2866 UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2867 UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2868 UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2869 UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2870 UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2963 UCHAR ucASICMaxTemperature;
2964 UCHAR
2979 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2980 UCHAR ucDesign_ID; //Indicate what is the board design
2981 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2997 UCHAR ucASICMaxTemperature;
2998 UCHAR ucMinAllowedBL_Level;
2999 UCHAR ucPadding[2]; //Don't use them
3015 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
3016 UCHAR ucDesign_ID; //Indicate what is the board design
3017 UCHAR ucMemoryModule_ID; //Indicate what is the board design
3033 UCHAR ucASICMaxTemperature;
3034 UCHAR ucMinAllowedBL_Level;
3035 UCHAR ucPadding[2]; //Don't use them
3052 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
3053 UCHAR ucDesign_ID; //Indicate what is the board design
3054 UCHAR ucMemoryModule_ID; //Indicate what is the board design
3070 UCHAR ucASICMaxTemperature;
3071 UCHAR ucMinAllowedBL_Level;
3090 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
3091 UCHAR ucDesign_ID; //Indicate what is the board design
3092 UCHAR ucMemoryModule_ID; //Indicate what is the board design
3109 UCHAR ucReserved1; //Was ucASICMaxTemperature;
3110 UCHAR ucMinAllowedBL_Level;
3130 UCHAR ucMemoryModule_ID; //Indicate what is the board design
3131 UCHAR ucReserved4[3];
3141 UCHAR ucEMBEDDED_CAP:2; // Bit[1:0] Embedded feature level
3142 UCHAR ucReserved:2; // Bit[3:2] Reserved
3143 UCHAR ucBRANDING_ID:4; // Bit[7:4] Branding ID
3159 UCHAR ucReserved3; //Was ucASICMaxTemperature;
3160 UCHAR ucMinAllowedBL_Level;
3166 UCHAR ucRemoteDisplayConfig;
3167 UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input
3178 UCHAR ucMemoryModule_ID; //Indicate what is the board design
3179 UCHAR ucCoolingSolution_ID; //0: Air cooling; 1: Liquid cooling ... [COOLING_SOLUTION]
3181 UCHAR ucReserved9;
3209 UCHAR ucNumberOfCyclesInPeriodHi;
3210 UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
3224 UCHAR ucMaxNBVoltage;
3225 UCHAR ucMinNBVoltage;
3226 UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
3227 UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod
3228 UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime
3229 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit
3230 UCHAR ucMaxNBVoltageHigh;
3231 UCHAR ucMinNBVoltageHigh;
3288 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
3289 UCHAR ucUMAChannelNumber;
3290 UCHAR ucDockingPinBit;
3291 UCHAR ucDockingPinPolarity;
3464 UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD
3465 UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD
3472 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
3473 UCHAR ucUMAChannelNumber;
3663 UCHAR bfHW_Capable:1;
3664 UCHAR bfHW_EngineID:3;
3665 UCHAR bfI2C_LineMux:4;
3667 UCHAR bfI2C_LineMux:4;
3668 UCHAR bfHW_EngineID:3;
3669 UCHAR bfHW_Capable:1;
3676 UCHAR ucAccess;
3694 UCHAR ucClkMaskShift;
3695 UCHAR ucClkEnShift;
3696 UCHAR ucClkY_Shift;
3697 UCHAR ucClkA_Shift;
3698 UCHAR ucDataMaskShift;
3699 UCHAR ucDataEnShift;
3700 UCHAR ucDataY_Shift;
3701 UCHAR ucDataA_Shift;
3702 UCHAR ucReserved1;
3703 UCHAR ucReserved2;
3812 UCHAR ucH_Border; // From DFP EDID
3813 UCHAR ucV_Border;
3814 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
3815 UCHAR ucPadding[3];
3832 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
3833 UCHAR ucOverscanRight; // right
3834 UCHAR ucOverscanLeft; // left
3835 UCHAR ucOverscanBottom; // bottom
3836 UCHAR ucOverscanTop; // top
3837 UCHAR ucReserved;
3864 UCHAR ucInternalModeNumber;
3865 UCHAR ucRefreshRate;
3881 UCHAR ucHBorder;
3882 UCHAR ucVBorder;
3884 UCHAR ucInternalModeNumber;
3885 UCHAR ucRefreshRate;
3907 UCHAR ucPowerSequenceDigOntoDEin10Ms;
3908 UCHAR ucPowerSequenceDEtoBLOnin10Ms;
3909 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
3913 UCHAR ucPanelDefaultRefreshRate;
3914 UCHAR ucPanelIdentification;
3915 UCHAR ucSS_Id;
3927 UCHAR ucPowerSequenceDigOntoDEin10Ms;
3928 UCHAR ucPowerSequenceDEtoBLOnin10Ms;
3929 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
3933 UCHAR ucPanelDefaultRefreshRate;
3934 UCHAR ucPanelIdentification;
3935 UCHAR ucSS_Id;
3938 UCHAR ucLCDPanel_SpecialHandlingCap;
3939 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
3940 UCHAR ucReserved[2];
3980 UCHAR ucSupportedRefreshRate;
3981 UCHAR ucMinRefreshRateForDRR;
4001 UCHAR ucLCD_Misc; // Reorganized in V13
4007 UCHAR ucPanelDefaultRefreshRate;
4008 UCHAR ucPanelIdentification;
4009 UCHAR ucSS_Id;
4012 UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13
4017 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
4020 UCHAR ucPowerSequenceDIGONtoDE_in4Ms;
4021 UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms;
4022 UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms;
4023 UCHAR ucPowerSequenceDEtoDIGON_in4Ms;
4025 UCHAR ucOffDelay_in4Ms;
4026 UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms;
4027 UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms;
4028 UCHAR ucReserved1;
4030 UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh
4031 UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h
4032 UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h
4033 UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h
4036 UCHAR uceDPToLVDSRxId;
4037 UCHAR ucLcdReservd;
4084 UCHAR ucRecordType;
4091 UCHAR ucRecordType;
4092 UCHAR ucRTSValue;
4099 UCHAR ucRecordType;
4110 UCHAR ucRecordType;
4111 UCHAR ucFakeEDIDLength; // = 128 means EDID length is 128 bytes, otherwise the EDID length = ucFakeEDIDLength*128
4112 UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements.
4117 UCHAR ucRecordType;
4137 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD
4138 UCHAR ucSS_Step;
4139 UCHAR ucSS_Delay;
4140 UCHAR ucSS_Id;
4141 UCHAR ucRecommendedRef_Div;
4142 UCHAR ucSS_Range; //it was reserved for V11
4200 UCHAR ucTV_SuppportedStandard;
4201 UCHAR ucTV_BootUpDefaultStandard;
4202 UCHAR ucExt_TV_ASIC_ID;
4203 UCHAR ucExt_TV_ASIC_SlaveAddr;
4209 UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1
4210 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane
4211 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
4212 UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec)
4366 UCHAR ucGpioPinBitShift;
4367 UCHAR ucGPIO_ID;
4408 UCHAR ucSettings;
4409 UCHAR ucReserved;
4451 UCHAR ucBitShift;
4452 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low
4454 UCHAR ucMiscInfo;
4455 UCHAR uc480i;
4456 UCHAR uc480p;
4457 UCHAR uc720p;
4458 UCHAR uc1080i;
4459 UCHAR ucLetterBoxMode;
4460 UCHAR ucReserved[3];
4461 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
4471 UCHAR ucMiscInfo;
4472 UCHAR uc480i;
4473 UCHAR uc480p;
4474 UCHAR uc720p;
4475 UCHAR uc1080i;
4476 UCHAR ucReserved;
4477 UCHAR ucLetterBoxMode;
4478 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
4532 UCHAR ucNumOfDispPath;
4533 UCHAR ucVersion;
4534 UCHAR ucPadding[2];
4548 UCHAR ucNumberOfObjects;
4549 UCHAR ucPadding[3];
4555 UCHAR ucNumberOfSrc;
4557 UCHAR ucNumberOfDst;
4593 UCHAR ucDP_Lane3_Source:2;
4594 UCHAR ucDP_Lane2_Source:2;
4595 UCHAR ucDP_Lane1_Source:2;
4596 UCHAR ucDP_Lane0_Source:2;
4598 UCHAR ucDP_Lane0_Source:2;
4599 UCHAR ucDP_Lane1_Source:2;
4600 UCHAR ucDP_Lane2_Source:2;
4601 UCHAR ucDP_Lane3_Source:2;
4613 UCHAR ucDVI_CLK_Source:2;
4614 UCHAR ucDVI_DATA0_Source:2;
4615 UCHAR ucDVI_DATA1_Source:2;
4616 UCHAR ucDVI_DATA2_Source:2;
4618 UCHAR ucDVI_DATA2_Source:2;
4619 UCHAR ucDVI_DATA1_Source:2;
4620 UCHAR ucDVI_DATA0_Source:2;
4621 UCHAR ucDVI_CLK_Source:2;
4630 UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT
4631 UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT
4634 UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping
4638 UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
4660 UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string
4662 UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0.
4663 UCHAR uc3DStereoPinId; // use for eDP panel
4664 UCHAR ucRemoteDisplayConfig;
4665 UCHAR uceDPToLVDSRxId;
4666 UCHAR ucFixDPVoltageSwing; // usCaps[1]=1, this indicate DP_LANE_SET value
4667 UCHAR Reserved[3]; // for potential expansion
4673 UCHAR ucRecordType; //An emun to indicate the record type
4674 UCHAR ucRecordSize; //The size of the whole record in byte
4708 UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC
4714 UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
4715 UCHAR ucPlugged_PinState;
4722 UCHAR ucProtectionFlag;
4723 UCHAR ucReserved;
4736 UCHAR ucNumberOfDevice;
4737 UCHAR ucReserved;
4745 UCHAR ucConfigGPIOID;
4746 UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in
4747 UCHAR ucFlowinGPIPID;
4748 UCHAR ucExtInGPIPID;
4754 UCHAR ucCTL1GPIO_ID;
4755 UCHAR ucCTL1GPIOState; //Set to 1 when it's active high
4756 UCHAR ucCTL2GPIO_ID;
4757 UCHAR ucCTL2GPIOState; //Set to 1 when it's active high
4758 UCHAR ucCTL3GPIO_ID;
4759 UCHAR ucCTL3GPIOState; //Set to 1 when it's active high
4760 UCHAR ucCTLFPGA_IN_ID;
4761 UCHAR ucPadding[3];
4767 UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
4768 UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected
4774 UCHAR ucTMSGPIO_ID;
4775 UCHAR
4776 UCHAR ucTCKGPIO_ID;
4777 UCHAR ucTCKGPIOState; //Set to 1 when it's active high
4778 UCHAR ucTDOGPIO_ID;
4779 UCHAR ucTDOGPIOState; //Set to 1 when it's active high
4780 UCHAR ucTDIGPIO_ID;
4781 UCHAR ucTDIGPIOState; //Set to 1 when it's active high
4782 UCHAR ucPadding[2];
4789 UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table
4790 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
4796 UCHAR ucFlags; // Future expnadibility
4797 UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object
4829 UCHAR ucPadding[2];
4891 UCHAR ucFlowCntlGpioId;
4892 UCHAR ucSwapCntlGpioId;
4893 UCHAR ucConnectedDvoBundle;
4894 UCHAR ucPadding;
4906 UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A
4907 UCHAR ucReserved;
4914 UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state
4915 UCHAR ucMuxControlPin;
4916 UCHAR ucMuxState[2]; //for alligment purpose
4922 UCHAR ucMuxType;
4923 UCHAR ucMuxControlPin;
4924 UCHAR ucMuxState[2]; //for alligment purpose
4934 UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table
4960 UCHAR ucMaxTmdsClkRateIn2_5Mhz;
4961 UCHAR ucReserved;
4968 UCHAR ucConnectorType;
4969 UCHAR ucPosition;
4983 UCHAR ucLength;
4984 UCHAR ucWidth;
4985 UCHAR ucConnNum;
4986 UCHAR ucReserved;
4998 UCHAR ucNumOfVoltageEntries;
4999 UCHAR ucBytesPerVoltageEntry;
5000 UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit
5001 UCHAR ucDefaultVoltageEntry;
5002 UCHAR ucVoltageControlI2cLine;
5003 UCHAR ucVoltageControlAddress;
5004 UCHAR ucVoltageControlOffset;
5011 UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry
5019 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
5020 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv
5021 UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep
5022 UCHAR ucReserved;
5023 UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries
5034 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
5035 UCHAR ucReserved[3];
5041 UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine
5042 UCHAR ucVoltageControlI2cLine;
5043 UCHAR ucVoltageControlAddress;
5044 UCHAR ucVoltageControlOffset;
5046 UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff
5047 UCHAR ucReserved;
5079 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
5080 UCHAR ucSize; //Size of Object
5087 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
5088 UCHAR ucSize; //Size of Object
5107 UCHAR ucLeakageId;
5108 UCHAR ucReserved;
5113 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
5114 UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase
5145 UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id
5146 UCHAR ucVoltageControlI2cLine;
5147 UCHAR ucVoltageControlAddress;
5148 UCHAR ucVoltageControlOffset;
5149 UCHAR ucVoltageControlFlag; // Bit0: 0 - One byte data; 1 - Two byte data
5150 UCHAR ulReserved[3];
5161 UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode
5162 UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table
5163 UCHAR ucPhaseDelay; // phase delay in unit of micro second
5164 UCHAR ucReserved;
5172 UCHAR ucLeakageCntlId; // default is 0
5173 UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table
5174 UCHAR ucReserved[2];
5190 UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31
5191 UCHAR ucSVCGpioId; //0~31 indicate GPIO0~31
5200 UCHAR ucMergedVType; // VDDC/VDCCI/....
5201 UCHAR ucReserved[3];
5209 UCHAR ucDPMTblVIndex; // Voltage Index in SMC_DPM_Table structure VddcTable/VddGfxTable
5210 UCHAR ucDPMState; // DPMState0~7
5238 UCHAR ucProfileId;
5239 UCHAR ucReserved;
5260 UCHAR ucLeakageBinNum; // indicate the entry number of LeakageId/Voltage Lut table
5263 UCHAR ucElbVDDC_Num;
5267 UCHAR ucElbVDDCI_Num;
5278 UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
5279 UCHAR ucEfuseLength; // Efuse bits length,
5288 UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
5289 UCHAR ucEfuseLength; // Efuse bits length,
5312 UCHAR ucLkgEfuseBitLSB;
5313 UCHAR ucLkgEfuseLength;
5353 UCHAR ucLkgEfuseBitLSB;
5354 UCHAR ucLkgEfuseLength;
5395 UCHAR ucLkgEfuseBitLSB;
5396 UCHAR ucLkgEfuseLength;
5454 UCHAR ucLkgEfuseBitLSB;
5455 UCHAR ucLkgEfuseLength;
5489 UCHAR ucSM_A0_sign;
5490 UCHAR ucSM_A1_sign;
5491 UCHAR ucSM_A2_sign;
5492 UCHAR ucSM_A3_sign;
5493 UCHAR ucSM_A4_sign;
5494 UCHAR ucSM_A5_sign;
5495 UCHAR ucSM_A6_sign;
5496 UCHAR ucSM_A7_sign;
5516 UCHAR ucLkgEfuseBitLSB; //Efuse Lkg_FT bit shift in 32bit DWORD
5517 UCHAR ucLkgEfuseLength; //Efuse Lkg_FT length
5533 UCHAR ucSM_A0_sign; //def="EVV_SM_A0_SIGN" descr="=0 SM_A0 is postive. =1: SM_A0 is negative" unit="1"/>
5534 UCHAR ucSM_A1_sign; //def="EVV_SM_A1_SIGN" descr="=0 SM_A1 is postive. =1: SM_A1 is negative" unit="1"/>
5535 UCHAR ucSM_A2_sign; //def="EVV_SM_A2_SIGN" descr="=0 SM_A2 is postive. =1: SM_A2 is negative" unit="1"/>
5536 UCHAR ucSM_A3_sign; //def="EVV_SM_A3_SIGN" descr="=0 SM_A3 is postive. =1: SM_A3 is negative" unit="1"/>
5537 UCHAR ucSM_A4_sign; //def="EVV_SM_A4_SIGN" descr="=0 SM_A4 is postive. =1: SM_A4 is negative" unit="1"/>
5538 UCHAR ucSM_A5_sign; //def="EVV_SM_A5_SIGN" descr="=0 SM_A5 is postive. =1: SM_A5 is negative" unit="1"/>
5539 UCHAR ucSM_A6_sign; //def="EVV_SM_A6_SIGN" descr="=0 SM_A6 is postive. =1: SM_A6 is negative" unit="1"/>
5540 UCHAR ucSM_A7_sign; //def="EVV_SM_A7_SIGN" descr="=0 SM_A7 is postive. =1: SM_A7 is negative" unit="1"/>
5560 UCHAR ucLkgEfuseBitLSB;
5561 UCHAR ucLkgEfuseLength;
5577 UCHAR ucSM_A0_sign;
5578 UCHAR ucSM_A1_sign;
5579 UCHAR ucSM_A2_sign;
5580 UCHAR ucSM_A3_sign;
5581 UCHAR ucSM_A4_sign;
5582 UCHAR ucSM_A5_sign;
5583 UCHAR ucSM_A6_sign;
5584 UCHAR ucSM_A7_sign;
5616 UCHAR ucEnableGB_VDROOP_TABLE_CKSOFF;
5617 UCHAR ucEnableGB_VDROOP_TABLE_CKSON;
5618 UCHAR ucEnableGB_FUSE_TABLE_CKSOFF;
5619 UCHAR ucEnableGB_FUSE_TABLE_CKSON;
5621 UCHAR ucEnableApplyAVFS_CKS_OFF_Voltage;
5622 UCHAR ucReserved;
5628 UCHAR ucVco_setting; // 1: 3-6GHz, 3: 2-4GHz
5629 UCHAR ucPostdiv; // divide by 2^n
5640 UCHAR ucSclkEntryNum; // for potential future extend, indicate the number of ATOM_SCLK_FCW_RANGE_ENTRY_V1
5641 UCHAR ucReserved[3];
5650 UCHAR GfxIpMinVer;
5651 UCHAR GfxIpMajVer;
5652 UCHAR max_shader_engines;
5653 UCHAR max_tile_pipes;
5654 UCHAR max_cu_per_sh;
5655 UCHAR max_sh_per_se;
5656 UCHAR max_backends_per_se;
5657 UCHAR max_texture_channel_caches;
5663 UCHAR ucPwrSrcId; // Power source
5664 UCHAR ucPwrSensorType; // GPIO, I2C or none
5665 UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id
5666 UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect
5667 UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect
5668 UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect
5669 UCHAR ucPwrSensActiveState; // high active or low active
5670 UCHAR ucReserve[3]; // reserve
5677 UCHAR asPwrbehave[16];
5730 UCHAR ucHtcTmpLmt;
5731 UCHAR ucHtcHystLmt;
5740 UCHAR ucMemoryType;
5741 UCHAR ucUMAChannelNumber;
5764 UCHAR ulBoostVid_2bit;
5765 UCHAR EnableBoost;
5768 UCHAR ucLvdsMisc;
5769 UCHAR ucLVDSReserved;
5928 UCHAR ucHtcTmpLmt;
5929 UCHAR ucHtcHystLmt;
5938 UCHAR ucMemoryType;
5939 UCHAR ucUMAChannelNumber;
5940 UCHAR strVBIOSMsg[40];
5962 UCHAR ulBoostVid_2bit;
5963 UCHAR EnableBoost;
5966 UCHAR ucLvdsMisc;
5967 UCHAR ucTravisLVDSVolAdjust;
5968 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
5969 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
5970 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
5971 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
5972 UCHAR ucLVDSOffToOnDelay_in4Ms;
5973 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
5974 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
5975 UCHAR ucMinAllowedBL_Level;
5981 UCHAR ucNBDPMEnable;
5982 UCHAR ucReserved[3];
5983 UCHAR ucDPMState0VclkFid;
5984 UCHAR ucDPMState0DclkFid;
5985 UCHAR ucDPMState1VclkFid;
5986 UCHAR ucDPMState1DclkFid;
5987 UCHAR ucDPMState2VclkFid;
5988 UCHAR ucDPMState2DclkFid;
5989 UCHAR ucDPMState3VclkFid;
5990 UCHAR ucDPMState3DclkFid;
6160 UCHAR ucHtcTmpLmt;
6161 UCHAR ucHtcHystLmt;
6169 UCHAR ucMemoryType;
6170 UCHAR ucUMAChannelNumber;
6171 UCHAR strVBIOSMsg[40];
6193 UCHAR ucLvdsMisc;
6194 UCHAR ucTravisLVDSVolAdjust;
6195 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
6196 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
6197 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
6198 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
6199 UCHAR ucLVDSOffToOnDelay_in4Ms;
6200 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
6201 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
6202 UCHAR ucMinAllowedBL_Level;
6361 UCHAR ucI2cRegIndex;
6362 UCHAR ucI2cRegVal;
6378 UCHAR ucHtcTmpLmt;
6379 UCHAR ucHtcHystLmt;
6387 UCHAR ucMemoryType;
6388 UCHAR ucUMAChannelNumber;
6389 UCHAR strVBIOSMsg[40];
6391 UCHAR ucExtHDMIReDrvSlvAddr;
6392 UCHAR ucExtHDMIReDrvRegNum;
6414 UCHAR ucLvdsMisc;
6415 UCHAR ucTravisLVDSVolAdjust;
6416 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
6417 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
6418 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
6419 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
6420 UCHAR ucLVDSOffToOnDelay_in4Ms;
6421 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
6422 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
6423 UCHAR ucMinAllowedBL_Level;
6430 UCHAR ucEDPv1_4VSMode;
6431 UCHAR ucReserved2;
6458 UCHAR ucProfileID; // SENSOR_PROFILES
6469 UCHAR ucID; // 0: Rear, 1: Front right of user, 2: Front left of user
6470 UCHAR strModuleName[8];
6476 UCHAR ucID; // 0: Rear, 1: Front
6477 UCHAR strName[8];
6501 UCHAR ucHtcTmpLmt;
6502 UCHAR ucHtcHystLmt;
6510 UCHAR ucMemoryType;
6511 UCHAR ucUMAChannelNumber;
6534 UCHAR ucLvdsMisc;
6535 UCHAR ucTravisLVDSVolAdjust;
6536 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
6537 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
6538 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
6539 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
6540 UCHAR ucLVDSOffToOnDelay_in4Ms;
6541 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
6542 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
6543 UCHAR ucMinAllowedBL_Level;
6551 UCHAR ucEDPv1_4VSMode;
6552 UCHAR ucReserved2;
6585 UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop"
6586 UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually
6594 UCHAR ucSSChipID; //SS chip being used
6595 UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip
6596 UCHAR ucNumOfI2CDataRecords; //number of data block
6618 UCHAR ucClockIndication; //Indicate which clock source needs SS
6619 UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread.
6620 UCHAR ucReserved[2];
6644 UCHAR ucClockIndication; //Indicate which clock source needs SS
6645 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
6646 UCHAR ucReserved[2];
6675 UCHAR ucClockIndication; //Indicate which clock source needs SS
6676 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
6677 UCHAR ucReserved[2];
7156 UCHAR ucAction; //not define yet
7157 UCHAR ucFbDiv_Hi; //Fbdiv Hi byte
7158 UCHAR ucFbDiv; //FB value
7159 UCHAR ucPostDiv; //Post div
7170 UCHAR ucGPIO_ID; //return value, read from GPIO pins
7171 UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update
7172 UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask
7173 UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write
7178 UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2
7179 UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION
7180 UCHAR ucTVStandard; //
7181 UCHAR ucPadding[1];
7194 UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset
7195 UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset
7196 UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2
7197 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
7210 UCHAR ucSurface; // Surface 1 or 2
7211 UCHAR ucPadding[3];
7218 UCHAR ucSurface; // Surface 1 or 2
7219 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
7220 UCHAR ucPadding[2];
7227 UCHAR ucSurface; // Surface 1 or 2
7228 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
7237 UCHAR ucColorDepth;
7238 UCHAR ucPixelFormat;
7239 UCHAR ucSurface; // Surface 1 or 2
7240 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
7241 UCHAR ucModeType;
7242 UCHAR ucReserved;
7283 UCHAR ucLutId;
7284 UCHAR ucAction;
7298 UCHAR ucInterruptId;
7299 UCHAR ucServiceId;
7300 UCHAR ucStatus;
7301 UCHAR ucReserved;
7324 UCHAR ucBitShift;
7325 UCHAR ucBitLength;
7338 UCHAR IOAccessSequence[256];
7374 UCHAR ucVMode_Num; //Video mode number
7375 UCHAR ucTV_Mode_Num; //Internal TV mode number
7393 UCHAR ucTV_Mode_Num;
7425 UCHAR ucMemoryType;
7426 UCHAR ucMemoryVendor;
7427 UCHAR ucAdjMCId;
7428 UCHAR ucDynClkId;
7458 UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf
7568 UCHAR ucRevision;
7569 UCHAR ucChecksum;
7570 UCHAR ucReserved1;
7571 UCHAR ucReserved2;
7589 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7590 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved;
7591 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender
7592 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
7593 UCHAR ucRow; // Number of Row,in power of 2;
7594 UCHAR ucColumn; // Number of Column,in power of 2;
7595 UCHAR ucBank; // Nunber of Bank;
7596 UCHAR ucRank; // Number of Rank, in power of 2
7597 UCHAR ucChannelNum; // Number of channel;
7598 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
7599 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
7600 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
7601 UCHAR ucReserved[2];
7616 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7617 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
7618 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
7619 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
7620 UCHAR ucRow; // Number of Row,in power of 2;
7621 UCHAR ucColumn; // Number of Column,in power of 2;
7622 UCHAR ucBank; // Nunber of Bank;
7623 UCHAR ucRank; // Number of Rank, in power of 2
7624 UCHAR ucChannelNum; // Number of channel;
7625 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
7626 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
7627 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
7628 UCHAR ucRefreshRateFactor;
7629 UCHAR ucReserved[3];
7644 UCHAR ucCL; // CAS latency
7645 UCHAR ucWL; // WRITE Latency
7646 UCHAR uctRAS; // tRAS
7647 UCHAR uctRC; // tRC
7648 UCHAR uctRFC; // tRFC
7649 UCHAR uctRCDR; // tRCDR
7650 UCHAR uctRCDW; // tRCDW
7651 UCHAR uctRP; // tRP
7652 UCHAR uctRRD; // tRRD
7653 UCHAR uctWR; // tWR
7654 UCHAR uctWTR; // tWTR
7655 UCHAR uctPDIX; // tPDIX
7656 UCHAR uctFAW; // tFAW
7657 UCHAR uctAOND; // tAOND
7661 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
7662 UCHAR ucReserved;
7674 UCHAR ucCL; // CAS latency
7675 UCHAR ucWL; // WRITE Latency
7676 UCHAR uctRAS; // tRAS
7677 UCHAR uctRC; // tRC
7678 UCHAR uctRFC; // tRFC
7679 UCHAR uctRCDR; // tRCDR
7680 UCHAR uctRCDW; // tRCDW
7681 UCHAR uctRP; // tRP
7682 UCHAR uctRRD; // tRRD
7683 UCHAR uctWR; // tWR
7684 UCHAR uctWTR; // tWTR
7685 UCHAR uctPDIX; // tPDIX
7686 UCHAR uctFAW; // tFAW
7687 UCHAR uctAOND; // tAOND
7688 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
7690 UCHAR uctCCDL; //
7691 UCHAR uctCRCRL; //
7692 UCHAR uctCRCWL; //
7693 UCHAR uctCKE; //
7694 UCHAR uctCKRSE; //
7695 UCHAR uctCKRSX; //
7696 UCHAR uctFAW32; //
7697 UCHAR ucMR5lo; //
7698 UCHAR ucMR5hi; //
7699 UCHAR ucTerminator;
7710 UCHAR ucCL; // CAS latency
7711 UCHAR ucWL; // WRITE Latency
7712 UCHAR uctRAS; // tRAS
7713 UCHAR uctRC; // tRC
7714 UCHAR uctRFC; // tRFC
7715 UCHAR uctRCDR; // tRCDR
7716 UCHAR uctRCDW; // tRCDW
7717 UCHAR uctRP; // tRP
7718 UCHAR uctRRD; // tRRD
7719 UCHAR uctWR; // tWR
7720 UCHAR uctWTR; // tWTR
7721 UCHAR uctPDIX; // tPDIX
7722 UCHAR uctFAW; // tFAW
7723 UCHAR uctAOND; // tAOND
7724 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
7726 UCHAR uctCCDL; //
7727 UCHAR uctCRCRL; //
7728 UCHAR uctCRCWL; //
7729 UCHAR uctCKE; //
7730 UCHAR uctCKRSE; //
7731 UCHAR uctCKRSX; //
7732 UCHAR uctFAW32; //
7733 UCHAR ucMR4lo; //
7734 UCHAR ucMR4hi; //
7735 UCHAR ucMR5lo; //
7736 UCHAR ucMR5hi; //
7737 UCHAR ucTerminator;
7738 UCHAR ucReserved;
7753 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
7754 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
7755 UCHAR ucRow; // Number of Row,in power of 2;
7756 UCHAR ucColumn; // Number of Column,in power of 2;
7757 UCHAR ucBank; // Nunber of Bank;
7758 UCHAR ucRank; // Number of Rank, in power of 2
7759 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8
7760 UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register )
7761 UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms
7762 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7763 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7764 UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc
7775 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7776 UCHAR ucChannelNum; // board dependent parameter:Number of channel;
7777 UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit
7778 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
7779 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
7780 UCHAR ucFlag; // To enable/disable functionalities based on memory type
7798 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7799 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7800 UCHAR ucChannelNum; // Number of channels present in this module config
7801 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7802 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7803 UCHAR ucFlag; // To enable/disable functionalities based on memory type
7804 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
7805 UCHAR ucVREFI; // board dependent parameter
7806 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
7807 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7808 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7810 UCHAR ucReserved[3];
7821 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
7822 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7823 UCHAR ucReserved2[2];
7840 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7841 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7842 UCHAR ucChannelNum; // Number of channels present in this module config
7843 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7844 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7845 UCHAR ucFlag; // To enable/disable functionalities based on memory type
7846 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
7847 UCHAR ucVREFI; // board dependent parameter
7848 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
7849 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7850 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7852 UCHAR ucReserved[3];
7857 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
7858 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7859 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
7860 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7872 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7873 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7874 UCHAR ucChannelNum; // Number of channels present in this module config
7875 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7876 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7877 UCHAR ucFlag; // To enable/disable functionalities based on memory type
7878 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
7879 UCHAR ucVREFI; // board dependent parameter
7880 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
7881 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7882 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7884 UCHAR ucReserved[3];
7889 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
7890 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7891 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
7892 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7903 UCHAR ucExtMemoryID; // Current memory module ID
7904 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
7905 UCHAR ucChannelNum; // Number of mem. channels supported in this module
7906 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
7907 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7908 UCHAR ucReserve; // In MC7x, the lower 4 bits are used as bit8-11 of memory size. In other MC code, it's not used.
7909 UCHAR ucMisc; // RANK_OF_THISMEMORY etc.
7910 UCHAR ucVREFI; // Not used.
7911 UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
7912 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7913 UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7915 UCHAR ucReserved;
7919 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
7920 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7921 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory
7922 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7934 UCHAR ucExtMemoryID; // Current memory module ID
7935 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
7936 UCHAR ucChannelNum; // Number of mem. channels supported in this module
7937 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
7938 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7939 UCHAR ucBankCol; // bit[3:2]= BANK ( =2:16bank, =1:8bank, =0:4bank ) bit[1:0]=Col ( =2: 10 bit, =1:9bit, =0:8bit )
7940 UCHAR ucMisc; // RANK_OF_THISMEMORY etc.
7941 UCHAR ucVREFI; // Not used.
7944 UCHAR ucMcTunningSetId; // MC phy registers set per.
7945 UCHAR ucRowNum;
7949 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
7950 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7951 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory
7952 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7964 UCHAR ucNumOfVRAMModule;
7974 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator
7975 UCHAR ucNumOfVRAMModule;
7989 UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3
7991 UCHAR ucReservde[4];
7992 UCHAR ucNumOfVRAMModule;
8004 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module
8005 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list
8006 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version
8007 UCHAR ucReserved;
8020 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module
8021 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list
8022 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version
8023 UCHAR ucMcPhyTileNum; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
8030 UCHAR ucByteRemapCh0;
8031 UCHAR ucByteRemapCh1;
8045 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator
8052 UCHAR ucTrainingLoop;
8053 UCHAR ucReserved[3];
8071 UCHAR ucControl;
8072 UCHAR ucData;
8073 UCHAR ucSatus;
8074 UCHAR ucTemp;
8082 UCHAR ucAct;
8083 UCHAR ucData;
8129 UCHAR VbeSignature[4];
8132 UCHAR Capabilities[4];
8156 UCHAR Reserved[222];
8157 UCHAR OemData[256];
8165 UCHAR RedBPP;
8166 UCHAR GreenBPP;
8167 UCHAR BlueBPP;
8168 UCHAR ReservedBPP;
8171 UCHAR Reserved[14];
8178 UCHAR WinAAttributes; // db ? ; window A attributes
8179 UCHAR WinBAttributes; // db ? ; window B attributes
8190 UCHAR XCharSize; // db ? ; character cell width in pixels
8191 UCHAR YCharSize; // db ? ; character cell height in pixels
8192 UCHAR NumberOfPlanes; // db ? ; number of memory planes
8193 UCHAR BitsPerPixel; // db ? ; bits per pixel
8194 UCHAR NumberOfBanks; // db ? ; number of banks
8195 UCHAR MemoryModel; // db ? ; memory model type
8196 UCHAR BankSize; // db ? ; bank size in KB
8197 UCHAR NumberOfImagePages;// db ? ; number of images
8198 UCHAR ReservedForPageFunction;//db 1 ; reserved for page function
8201 UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits
8202 UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask
8203 UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits
8204 UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask
8205 UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits
8206 UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask
8207 UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits
8208 UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask
8209 UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes
8218 UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes
8219 UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes
8220 UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes)
8221 UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes)
8222 UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes)
8223 UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes)
8224 UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes)
8225 UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes)
8226 UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes)
8227 UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes)
8229 UCHAR Reserved; // db 190 dup (0)
8285 UCHAR ucTransmitterCmdTblId;
8286 UCHAR ucConfig;
8287 UCHAR ucEncoderID; //available 1st encoder ( default )
8288 UCHAR ucOptionEncoderID; //available 2nd encoder ( optional )
8289 UCHAR uc2ndEncoderID;
8290 UCHAR ucReserved;
8305 UCHAR ucEncoderID;
8306 UCHAR ucEncoderConfig;
8332 UCHAR ucPpllId;
8333 UCHAR ucPpllAttribute;
8346 UCHAR ucTransmitterCmdTblId;
8347 UCHAR ucConfig;
8348 UCHAR ucEncoderID; // available 1st encoder ( default )
8349 UCHAR ucOptionEncoderID; // available 2nd encoder ( optional )
8350 UCHAR uc2ndEncoderID;
8351 UCHAR ucReserved;
8361 UCHAR ucDCERevision;
8362 UCHAR ucMaxDispEngineNum;
8363 UCHAR ucMaxActiveDispEngineNum;
8364 UCHAR ucMaxPPLLNum;
8365 UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE
8366 UCHAR ucDispCaps;
8367 UCHAR ucReserved[2];
8393 UCHAR ucChannelID;
8396 UCHAR ucReplyStatus;
8397 UCHAR ucDelay;
8399 UCHAR ucDataOutLen;
8400 UCHAR ucReserved;
8408 UCHAR ucChannelID;
8411 UCHAR ucReplyStatus;
8412 UCHAR ucDelay;
8414 UCHAR ucDataOutLen;
8415 UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
8427 UCHAR ucConfig; // for DP training command
8428 UCHAR ucI2cId; // use for GET_SINK_TYPE command
8430 UCHAR ucAction;
8431 UCHAR ucStatus;
8432 UCHAR ucLaneNum;
8433 UCHAR ucReserved[2];
8445 UCHAR ucAuxId;
8446 UCHAR ucAction;
8447 UCHAR ucSinkType; // Iput and Output parameters.
8448 UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
8449 UCHAR ucReserved[2];
8481 UCHAR ucI2CSpeed;
8484 UCHAR ucRegIndex;
8485 UCHAR ucStatus;
8488 UCHAR ucFlag;
8489 UCHAR ucTransBytes;
8490 UCHAR ucSlaveAddr;
8491 UCHAR ucLineNumber;
8506 UCHAR ucCmd; // Input: To tell which action to take
8507 UCHAR ucReserved[3];
8513 UCHAR ucReturnCode; // Output: Return value base on action was taken
8514 UCHAR ucReserved[3];
8536 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ...
8537 UCHAR ucReserved[3];
8596 UCHAR ucStartBit;
8597 UCHAR ucEndBit;
8602 UCHAR ucEncodeMode;
8603 UCHAR ucPhySel;
8619 UCHAR ucCondition2;
8636 UCHAR ucEncodeMode;
8637 UCHAR ucPhySel;
8643 UCHAR ucEncodeMode;
8644 UCHAR ucPhySel;
8651 UCHAR ucGfxBlkId; //GFX blk id to be harvested, like CU, RB or PRIM
8652 UCHAR ucReserved; //reserved
8653 UCHAR ucActiveUnitNumPerSH; //requested active CU/RB/PRIM number per shader array
8654 UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array
8664 UCHAR PciRomSignature[2];
8665 UCHAR ucPciRomSizeIn512bytes;
8666 UCHAR ucJumpCoreMainInitBIOS;
8668 UCHAR PciReservedSpace[18];
8670 UCHAR Rsvd1d_1a[4];
8672 UCHAR CheckSum[14];
8673 UCHAR ucBiosMsgNumber;
8677 UCHAR ucSpeicalPostImageSizeIn512Bytes;
8678 UCHAR Rsved47_45[3];
8680 UCHAR Rsved4f_4a[6];
8682 UCHAR ucJumpCoreXFuncFarHandler;
8684 UCHAR ucRsved67;
8685 UCHAR ucJumpCoreVFuncFarHandler;
8687 UCHAR Rsved6d_6b[3];
8731 UCHAR ucDAC1_BG_Adjustment;
8732 UCHAR ucDAC1_DAC_Adjustment;
8735 UCHAR ucDAC2_CRT2_BG_Adjustment;
8736 UCHAR ucDAC2_CRT2_DAC_Adjustment;
8739 UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
8740 UCHAR ucDAC2_NTSC_BG_Adjustment;
8741 UCHAR ucDAC2_NTSC_DAC_Adjustment;
8744 UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
8745 UCHAR ucDAC2_CV_BG_Adjustment;
8746 UCHAR ucDAC2_CV_DAC_Adjustment;
8749 UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
8750 UCHAR ucDAC2_PAL_BG_Adjustment;
8751 UCHAR ucDAC2_PAL_DAC_Adjustment;
8782 UCHAR bfConnectorType:4;
8783 UCHAR bfAssociatedDAC:4;
8785 UCHAR bfAssociatedDAC:4;
8786 UCHAR bfConnectorType:4;
8793 UCHAR ucAccess;
8814 UCHAR ucIntSrcBitmap;
8840 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
8841 UCHAR ucPLL_DutyCycle; // PLL duty cycle control
8842 UCHAR ucPLL_VCO_Gain; // PLL VCO gain control
8843 UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control
8859 UCHAR ucTVStandard; //Same as TV standards defined above,
8860 UCHAR ucPadding[1];
8865 UCHAR ucAttribute; //Same as other digital encoder attributes defined above
8866 UCHAR ucPadding[1];
8880 UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only.
8881 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
8905 UCHAR ucXtransimitterID;
8906 UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported
8907 UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters
8909 UCHAR ucMasterAddress; // Address to control Master xTMDS Chip
8910 UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip
8915 UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off
8916 UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX....
8917 UCHAR ucPadding[2];
8985 UCHAR ucVoltageDropIndex; // index to GPIO table
8986 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
8987 UCHAR ucMinTemperature;
8988 UCHAR ucMaxTemperature;
8989 UCHAR ucNumPciELanes; // number of PCIE lanes
9000 UCHAR ucVoltageDropIndex; // index to GPIO table
9001 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
9002 UCHAR ucMinTemperature;
9003 UCHAR ucMaxTemperature;
9004 UCHAR ucNumPciELanes; // number of PCIE lanes
9015 UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table
9016 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
9017 UCHAR ucMinTemperature;
9018 UCHAR ucMaxTemperature;
9019 UCHAR ucNumPciELanes; // number of PCIE lanes
9020 UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table
9041 UCHAR ucOverdriveThermalController;
9042 UCHAR ucOverdriveI2cLine;
9043 UCHAR ucOverdriveIntBitmap;
9044 UCHAR ucOverdriveControllerAddress;
9045 UCHAR ucSizeOfPowerModeEntry;
9046 UCHAR ucNumOfPowerModeEntries;
9053 UCHAR ucOverdriveThermalController;
9054 UCHAR ucOverdriveI2cLine;
9055 UCHAR ucOverdriveIntBitmap;
9056 UCHAR ucOverdriveControllerAddress;
9057 UCHAR ucSizeOfPowerModeEntry;
9058 UCHAR ucNumOfPowerModeEntries;
9065 UCHAR ucOverdriveThermalController;
9066 UCHAR ucOverdriveI2cLine;
9067 UCHAR ucOverdriveIntBitmap;
9068 UCHAR ucOverdriveControllerAddress;
9069 UCHAR ucSizeOfPowerModeEntry;
9070 UCHAR ucNumOfPowerModeEntries;
9205 UCHAR ucRevision; // Holes set revision
9206 UCHAR ucAlgorithm; // Hash algorithm
9207 UCHAR ucSignatureType; // Signature type ( 0 - no signature, 1 - test, 2 - production )
9208 UCHAR
9218 UCHAR ucholesNo; // number of holes that follow
9234 UCHAR Revision;
9235 UCHAR Checksum;
9236 UCHAR OemId[6];
9237 UCHAR OemTableId[8]; //UINT64 OemTableId;
9258 UCHAR TableUUID[16]; //0x24
9279 UCHAR VbiosContent[1];
9284 UCHAR Lib1Content[1];
Indexes created Thu Oct 02 10:09:58 GMT 2025