Lines Matching defs:ULONG
46 #ifndef ULONG
47 typedef unsigned long ULONG;
264 ULONG ulPSPDirTableOffset;
429 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
430 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
431 ULONG ulClockFreq:24;
433 ULONG ulClockFreq:24;
434 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
435 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
442 ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
451 ULONG ulClock; //When return, [23:0] return real clock
480 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
481 ULONG ulClockFreq:24; // in unit of 10kHz
483 ULONG ulClockFreq:24; // in unit of 10kHz
484 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
499 ULONG ulClockParams; //ULONG access for BE
519 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly
520 ULONG ulClock:24; //Input= target clock, output = actual clock
522 ULONG ulClock:24; //Input= target clock, output = actual clock
523 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly
532 ULONG ulClockParams; //ULONG access for BE
549 ULONG ulReserved[2];
574 ULONG ulReserved[5];
607 ULONG ulClock;
634 ULONG ulReserved;
649 ULONG ulReserved[2];
657 ULONG ulMemoryClock;
658 ULONG ulReserved;
668 ULONG ulReserved;
689 ULONG ulTargetEngineClock; //In 10Khz unit
694 ULONG ulTargetEngineClock; //In 10Khz unit
700 ULONG ulTargetEngineClock; //In 10Khz unit
710 ULONG ulTargetMemoryClock; //In 10Khz unit
715 ULONG ulTargetMemoryClock; //In 10Khz unit
724 ULONG ulDefaultEngineClock; //In 10Khz unit
725 ULONG ulDefaultMemoryClock; //In 10Khz unit
736 ULONG ulClkFreqIn10Khz:24;
737 ULONG ucClkFlag:8;
749 ULONG ulReserved[8];
777 ULONG ulReserved[4];
806 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC
1089 ULONG ulPixelClock; // Pixel Clock in 10Khz
1101 ULONG ulSymClock; // Symbol Clock in 10Khz
1115 ULONG ulReserved[2];
1123 ULONG ulReserved[2];
1571 ULONG ulSymClock; // Symbol Clock in 10Khz
1576 ULONG ulReserved;
1649 ULONG ulReserved[2];
1935 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1950 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1952 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1955 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1957 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1966 ULONG ulDispEngClkFreq; // dispclk frequency
1983 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
2019 ULONG ulPixelClock; // target the pixel clock to drive the CRTC timing in unit of 100Hz.
2034 ULONG ulReserved;
2056 ULONG ulDISPClkFreq; // target DISPCLK frquency in unit of 10kHz, return real DISPCLK frequency. when ucFlag[1]=1, in unit of 100Hz.
2067 ULONG ulReserved[2];
2078 ULONG ulDCEClkFreq; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.
2108 ULONG ulReserved[2];
2157 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc
2188 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
2197 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
2378 ULONG ulTargetMemoryClock; //In 10Khz unit
2675 ULONG ulReserved;
2681 ULONG ulVotlageGpioState;
2682 ULONG ulVoltageGPioMask;
2690 ULONG ulReseved;
2714 ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table
2736 ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table
2737 ULONG ulReserved[3];
2743 ULONG ulVoltageLevel; // real voltage level in unit of 0.01mv
2744 ULONG ulReserved[4];
2753 ULONG ulDfsPllOutputFreq:24;
2754 ULONG ucDfsDivider:8;
2759 ULONG ulDfsOutputFreq;
2844 ULONG ulSignature; // HW info table signature string "$ATI"
2858 ULONG ulSignature; // MM info table signature sting "$MMT"
2953 ULONG ulFirmwareRevision;
2954 ULONG ulDefaultEngineClock; //In 10Khz unit
2955 ULONG ulDefaultMemoryClock; //In 10Khz unit
2956 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2957 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2958 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2959 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2960 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2961 ULONG ulASICMaxEngineClock; //In 10Khz unit
2962 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2965 ULONG aulReservedForBIOS[3]; //Don't use them
2987 ULONG ulFirmwareRevision;
2988 ULONG ulDefaultEngineClock; //In 10Khz unit
2989 ULONG ulDefaultMemoryClock; //In 10Khz unit
2990 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2991 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2992 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2993 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2994 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2995 ULONG ulASICMaxEngineClock; //In 10Khz unit
2996 ULONG ulASICMaxMemoryClock; //In 10Khz unit
3000 ULONG aulReservedForBIOS[2]; //Don't use them
3001 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3023 ULONG ulFirmwareRevision;
3024 ULONG ulDefaultEngineClock; //In 10Khz unit
3025 ULONG ulDefaultMemoryClock; //In 10Khz unit
3026 ULONG ulDriverTargetEngineClock; //In 10Khz unit
3027 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
3028 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3029 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3030 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3031 ULONG ulASICMaxEngineClock; //In 10Khz unit
3032 ULONG ulASICMaxMemoryClock; //In 10Khz unit
3036 ULONG aulReservedForBIOS; //Don't use them
3037 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
3038 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3060 ULONG ulFirmwareRevision;
3061 ULONG ulDefaultEngineClock; //In 10Khz unit
3062 ULONG ulDefaultMemoryClock; //In 10Khz unit
3063 ULONG ulDriverTargetEngineClock; //In 10Khz unit
3064 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
3065 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3066 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3067 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3068 ULONG ulASICMaxEngineClock; //In 10Khz unit
3069 ULONG ulASICMaxMemoryClock; //In 10Khz unit
3075 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
3076 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3099 ULONG ulFirmwareRevision;
3100 ULONG ulDefaultEngineClock; //In 10Khz unit
3101 ULONG ulDefaultMemoryClock; //In 10Khz unit
3102 ULONG ulReserved1;
3103 ULONG ulReserved2;
3104 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3105 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3106 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3107 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock
3108 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit
3114 ULONG ulReserved4; //Was ulAsicMaximumVoltage
3115 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3149 ULONG ulFirmwareRevision;
3150 ULONG ulDefaultEngineClock; //In 10Khz unit
3151 ULONG ulDefaultMemoryClock; //In 10Khz unit
3152 ULONG ulSPLL_OutputFreq; //In 10Khz unit
3153 ULONG ulGPUPLL_OutputFreq; //In 10Khz unit
3154 ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
3155 ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
3156 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3157 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ?
3158 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage.
3164 ULONG ulReserved4; //Was ulAsicMaximumVoltage
3165 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3168 ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input
3169 ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output
3184 ULONG ulReserved10[3]; // New added comparing to previous version
3205 ULONG ulBootUpEngineClock; //in 10kHz unit
3206 ULONG ulBootUpMemoryClock; //in 10kHz unit
3207 ULONG ulMaxSystemMemoryClock; //in 10kHz unit
3208 ULONG ulMinSystemMemoryClock; //in 10kHz unit
3214 ULONG ulReserved[2];
3277 ULONG ulBootUpEngineClock; //in 10kHz unit
3278 ULONG ulReserved1[2]; //must be 0x0 for the reserved
3279 ULONG ulBootUpUMAClock; //in 10kHz unit
3280 ULONG ulBootUpSidePortClock; //in 10kHz unit
3281 ULONG ulMinSidePortClock; //in 10kHz unit
3282 ULONG ulReserved2[6]; //must be 0x0 for the reserved
3283 ULONG ulSystemConfig; //see explanation below
3284 ULONG ulBootUpReqDisplayVector;
3285 ULONG ulOtherDisplayMisc;
3286 ULONG ulDDISlot1Config;
3287 ULONG ulDDISlot2Config;
3292 ULONG ulDockingPinCFGInfo;
3293 ULONG ulCPUCapInfo;
3298 ULONG ulHTLinkFreq; //in 10Khz
3305 ULONG ulHighVoltageHTLinkFreq; // in 10Khz
3306 ULONG ulLowVoltageHTLinkFreq; // in 10Khz
3313 ULONG ulReserved3[96]; //must be 0x0
3451 ULONG ulBootUpEngineClock; //in 10kHz unit
3452 ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK.
3453 ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge
3454 ULONG ulBootUpUMAClock; //in 10kHz unit
3455 ULONG ulReserved1[8]; //must be 0x0 for the reserved
3456 ULONG ulBootUpReqDisplayVector;
3457 ULONG ulOtherDisplayMisc;
3458 ULONG ulReserved2[4]; //must be 0x0 for the reserved
3459 ULONG ulSystemConfig; //TBD
3460 ULONG ulCPUCapInfo; //TBD
3466 ULONG ulReserved3[4]; //must be 0x0 for the reserved
3467 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition
3468 ULONG ulDDISlot2Config;
3469 ULONG ulDDISlot3Config;
3470 ULONG ulDDISlot4Config;
3471 ULONG ulReserved4[4]; //must be 0x0 for the reserved
3475 ULONG ulReserved5[4]; //must be 0x0 for the reserved
3476 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default
3477 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback
3478 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications
3479 ULONG ulReserved6[61]; //must be 0x0
3490 ULONG ulMCUcodeRomStartAddr;
3491 ULONG ulMCUcodeLength;
3492 ULONG ulSMCUcodeRomStartAddr;
3493 ULONG ulSMCUcodeLength;
3494 ULONG ulRLCVUcodeRomStartAddr;
3495 ULONG ulRLCVUcodeLength;
3496 ULONG ulTOCUcodeStartAddr;
3497 ULONG ulTOCUcodeLength;
3498 ULONG ulSMCPatchTableStartAddr;
3499 ULONG ulSmcPatchTableLength;
3500 ULONG ulSystemFlag;
4000 ULONG ulReserved0;
4038 ULONG ulReserved[2];
4335 ULONG ulStartAddrUsedByFirmware;
4349 ULONG ulStartAddrUsedByFirmware;
4728 ULONG ulACPIDeviceEnum; //Reserved for now
4828 ULONG ulStrengthControl; // DVOA strength control for CF
5130 ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register
5165 ULONG ulGpioMaskVal; // GPIO Mask value
5175 ULONG ulMaxVoltageLevel;
5192 ULONG ulReserved;
5207 ULONG ulDPMSclk; // DPM state SCLK
5280 ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number
5281 ULONG ulEfuseEncodeAverage; // Average = ( Max + Min )/2
5290 ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number
5291 ULONG ulEfuseMin; // Min
5298 ULONG ulEvvDerateTdp;
5299 ULONG ulEvvDerateTdc;
5300 ULONG ulBoardCoreTemp;
5301 ULONG ulMaxVddc;
5302 ULONG ulMinVddc;
5303 ULONG ulLoadLineSlop;
5304 ULONG ulLeakageTemp;
5305 ULONG ulLeakageVoltage;
5314 ULONG ulLkgEncodeLn_MaxDivMin;
5315 ULONG ulLkgEncodeMax;
5316 ULONG ulLkgEncodeMin;
5317 ULONG ulEfuseLogisticAlpha;
5340 ULONG ulEvvLkgFactor;
5341 ULONG ulBoardCoreTemp;
5342 ULONG ulMaxVddc;
5343 ULONG ulMinVddc;
5344 ULONG ulLoadLineSlop;
5345 ULONG ulLeakageTemp;
5346 ULONG ulLeakageVoltage;
5355 ULONG ulLkgEncodeLn_MaxDivMin;
5356 ULONG ulLkgEncodeMax;
5357 ULONG ulLkgEncodeMin;
5358 ULONG ulEfuseLogisticAlpha;
5367 ULONG ulTdpDerateDPM0;
5368 ULONG ulTdpDerateDPM1;
5369 ULONG ulTdpDerateDPM2;
5370 ULONG ulTdpDerateDPM3;
5371 ULONG ulTdpDerateDPM4;
5372 ULONG ulTdpDerateDPM5;
5373 ULONG ulTdpDerateDPM6;
5374 ULONG ulTdpDerateDPM7;
5382 ULONG ulEvvLkgFactor;
5383 ULONG ulBoardCoreTemp;
5384 ULONG ulMaxVddc;
5385 ULONG ulMinVddc;
5386 ULONG ulLoadLineSlop;
5387 ULONG ulLeakageTemp;
5388 ULONG ulLeakageVoltage;
5397 ULONG ulLkgEncodeLn_MaxDivMin;
5398 ULONG ulLkgEncodeMax;
5399 ULONG ulLkgEncodeMin;
5400 ULONG ulEfuseLogisticAlpha;
5413 ULONG ulTdpDerateDPM0;
5414 ULONG ulTdpDerateDPM1;
5415 ULONG ulTdpDerateDPM2;
5416 ULONG ulTdpDerateDPM3;
5417 ULONG ulTdpDerateDPM4;
5418 ULONG ulTdpDerateDPM5;
5419 ULONG ulTdpDerateDPM6;
5420 ULONG ulTdpDerateDPM7;
5422 ULONG ulRoAlpha;
5423 ULONG ulRoBeta;
5424 ULONG ulRoGamma;
5425 ULONG ulRoEpsilon;
5426 ULONG ulATermRo;
5427 ULONG ulBTermRo;
5428 ULONG ulCTermRo;
5429 ULONG ulSclkMargin;
5430 ULONG ulFmaxPercent;
5431 ULONG ulCRPercent;
5432 ULONG ulSFmaxPercent;
5433 ULONG ulSCRPercent;
5434 ULONG ulSDCMargine;
5441 ULONG ulEvvLkgFactor;
5442 ULONG ulBoardCoreTemp;
5443 ULONG ulMaxVddc;
5444 ULONG ulMinVddc;
5445 ULONG ulLoadLineSlop;
5446 ULONG ulLeakageTemp;
5447 ULONG ulLeakageVoltage;
5456 ULONG ulLkgEncodeLn_MaxDivMin;
5457 ULONG ulLkgEncodeMax;
5458 ULONG ulLkgEncodeMin;
5459 ULONG ulEfuseLogisticAlpha;
5468 ULONG ulTdpDerateDPM0;
5469 ULONG ulTdpDerateDPM1;
5470 ULONG ulTdpDerateDPM2;
5471 ULONG ulTdpDerateDPM3;
5472 ULONG ulTdpDerateDPM4;
5473 ULONG ulTdpDerateDPM5;
5474 ULONG ulTdpDerateDPM6;
5475 ULONG ulTdpDerateDPM7;
5477 ULONG ulEvvDefaultVddc;
5478 ULONG ulEvvNoCalcVddc;
5481 ULONG ulSM_A0;
5482 ULONG ulSM_A1;
5483 ULONG ulSM_A2;
5484 ULONG ulSM_A3;
5485 ULONG ulSM_A4;
5486 ULONG ulSM_A5;
5487 ULONG ulSM_A6;
5488 ULONG ulSM_A7;
5497 ULONG ulMargin_RO_a;
5498 ULONG ulMargin_RO_b;
5499 ULONG ulMargin_RO_c;
5500 ULONG ulMargin_fixed;
5501 ULONG ulMargin_Fmax_mean;
5502 ULONG ulMargin_plat_mean;
5503 ULONG ulMargin_Fmax_sigma;
5504 ULONG ulMargin_plat_sigma;
5505 ULONG ulMargin_DC_sigma;
5506 ULONG ulReserved[8]; // Reserved for future ASIC
5513 ULONG ulMaxVddc; //Maximum voltage for all parts, in unit of 0.01mv
5514 ULONG ulMinVddc; //Minimum voltage for all parts, in unit of 0.01mv
5518 ULONG ulLkgEncodeLn_MaxDivMin; //value of ln(Max_Lkg_Ft/Min_Lkg_Ft ) in unit of 0.00001 ( unit=100000 )
5519 ULONG ulLkgEncodeMax; //Maximum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 )
5520 ULONG ulLkgEncodeMin; //Minimum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 )
5522 ULONG ulEvvDefaultVddc; //def="EVV_DEFAULT_VDDC" descr="return default VDDC(v) when Efuse not cut" unit="100000"/>
5523 ULONG ulEvvNoCalcVddc; //def="EVV_NOCALC_VDDC" descr="return VDDC(v) when Calculation is bad" unit="100000"/>
5524 ULONG ulSpeed_Model; //def="EVV_SPEED_MODEL" descr="0 = Greek model, 1 = multivariate model" unit="1"/>
5525 ULONG ulSM_A0; //def="EVV_SM_A0" descr="Leakage coeff(Multivariant Mode)." unit="100000"/>
5526 ULONG ulSM_A1; //def="EVV_SM_A1" descr="Leakage/SCLK coeff(Multivariant Mode)." unit="1000000"/>
5527 ULONG ulSM_A2; //def="EVV_SM_A2" descr="Alpha( Greek Mode ) or VDDC/SCLK coeff(Multivariant Mode)." unit="100000"/>
5528 ULONG ulSM_A3; //def="EVV_SM_A3" descr="Beta( Greek Mode ) or SCLK coeff(Multivariant Mode)." unit="100000"/>
5529 ULONG ulSM_A4; //def="EVV_SM_A4" descr="VDDC^2/SCLK coeff(Multivariant Mode)." unit="100000"/>
5530 ULONG ulSM_A5; //def="EVV_SM_A5" descr="VDDC^2 coeff(Multivariant Mode)." unit="100000"/>
5531 ULONG ulSM_A6; //def="EVV_SM_A6" descr="Gamma( Greek Mode ) or VDDC coeff(Multivariant Mode)." unit="100000"/>
5532 ULONG ulSM_A7; //def="EVV_SM_A7" descr="Epsilon( Greek Mode ) or constant(Multivariant Mode)." unit="100000"/>
5541 ULONG ulMargin_RO_a; //def="EVV_MARGIN_RO_A" descr="A Term to represent RO equation in Ax2+Bx+C, unit=1"
5542 ULONG ulMargin_RO_b; //def="EVV_MARGIN_RO_B" descr="B Term to represent RO equation in Ax2+Bx+C, unit=1"
5543 ULONG ulMargin_RO_c; //def="EVV_MARGIN_RO_C" descr="C Term to represent RO equation in Ax2+Bx+C, unit=1"
5544 ULONG ulMargin_fixed; //def="EVV_MARGIN_FIXED" descr="Fixed MHz to add to SCLK margin, unit=1" unit="1"/>
5545 ULONG
5546 ULONG ulMargin_plat_mean; //def="EVV_MARGIN_PLAT_MEAN" descr="Percentage to add for platform mean margin unit=10000" unit="10000"/>
5547 ULONG ulMargin_Fmax_sigma; //def="EVV_MARGIN_FMAX_SIGMA" descr="Percentage to add for Fmax sigma margin unit=10000" unit="10000"/>
5548 ULONG ulMargin_plat_sigma; //def="EVV_MARGIN_PLAT_SIGMA" descr="Percentage to add for platform sigma margin unit=10000" unit="10000"/>
5549 ULONG ulMargin_DC_sigma; //def="EVV_MARGIN_DC_SIGMA" descr="Regulator DC tolerance margin (mV) unit=100" unit="100"/>
5550 ULONG ulReserved[12];
5557 ULONG ulMaxVddc;
5558 ULONG ulMinVddc;
5562 ULONG ulLkgEncodeLn_MaxDivMin;
5563 ULONG ulLkgEncodeMax;
5564 ULONG ulLkgEncodeMin;
5566 ULONG ulEvvDefaultVddc;
5567 ULONG ulEvvNoCalcVddc;
5568 ULONG ulSpeed_Model;
5569 ULONG ulSM_A0;
5570 ULONG ulSM_A1;
5571 ULONG ulSM_A2;
5572 ULONG ulSM_A3;
5573 ULONG ulSM_A4;
5574 ULONG ulSM_A5;
5575 ULONG ulSM_A6;
5576 ULONG ulSM_A7;
5585 ULONG ulMargin_RO_a;
5586 ULONG ulMargin_RO_b;
5587 ULONG ulMargin_RO_c;
5588 ULONG ulMargin_fixed;
5589 ULONG ulMargin_Fmax_mean;
5590 ULONG ulMargin_plat_mean;
5591 ULONG ulMargin_Fmax_sigma;
5592 ULONG ulMargin_plat_sigma;
5593 ULONG ulMargin_DC_sigma;
5594 ULONG ulLoadLineSlop;
5595 ULONG ulaTDClimitPerDPM[8];
5596 ULONG ulaNoCalcVddcPerDPM[8];
5597 ULONG ulAVFS_meanNsigma_Acontant0;
5598 ULONG ulAVFS_meanNsigma_Acontant1;
5599 ULONG ulAVFS_meanNsigma_Acontant2;
5603 ULONG ulGB_VDROOP_TABLE_CKSOFF_a0;
5604 ULONG ulGB_VDROOP_TABLE_CKSOFF_a1;
5605 ULONG ulGB_VDROOP_TABLE_CKSOFF_a2;
5606 ULONG ulGB_VDROOP_TABLE_CKSON_a0;
5607 ULONG ulGB_VDROOP_TABLE_CKSON_a1;
5608 ULONG ulGB_VDROOP_TABLE_CKSON_a2;
5609 ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_m1;
5611 ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_b;
5612 ULONG ulAVFSGB_FUSE_TABLE_CKSON_m1;
5614 ULONG ulAVFSGB_FUSE_TABLE_CKSON_b;
5627 ULONG ulMaxSclkFreq;
5696 ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table
5697 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
5704 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
5709 ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
5721 ULONG ulBootUpEngineClock;
5722 ULONG ulDentistVCOFreq;
5723 ULONG ulBootUpUMAClock;
5725 ULONG ulBootUpReqDisplayVector;
5726 ULONG ulOtherDisplayMisc;
5727 ULONG ulGPUCapInfo;
5728 ULONG ulSB_MMIO_Base_Addr;
5732 ULONG ulMinEngineClock;
5733 ULONG ulSystemConfig;
5734 ULONG ulCPUCapInfo;
5742 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];
5743 ULONG ulCSR_M3_ARB_CNTL_UVD[10];
5744 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];
5746 ULONG ulGMCRestoreResetTime;
5747 ULONG ulMinimumNClk;
5748 ULONG ulIdleNClk;
5749 ULONG ulDDR_DLL_PowerUpTime;
5750 ULONG ulDDR_PLL_PowerUpTime;
5759 ULONG SclkDpmBoostMargin;
5760 ULONG SclkDpmThrottleMargin;
5763 ULONG ulBoostEngineCLock;
5770 ULONG ulReserved3[15];
5884 ULONG ulPowerplayTable[128];
5891 ULONG uReserved:2;
5892 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts
5893 ULONG uCTDP_Value:14; // Override value in tens of milli watts
5894 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
5896 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
5897 ULONG uCTDP_Value:14; // Override value in tens of milli watts
5898 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts
5899 ULONG uReserved:2;
5906 ULONG TDP_config_all;
5919 ULONG ulBootUpEngineClock;
5920 ULONG ulDentistVCOFreq;
5921 ULONG ulBootUpUMAClock;
5923 ULONG ulBootUpReqDisplayVector;
5924 ULONG ulOtherDisplayMisc;
5925 ULONG ulGPUCapInfo;
5926 ULONG ulSB_MMIO_Base_Addr;
5930 ULONG ulMinEngineClock;
5931 ULONG ulSystemConfig;
5932 ULONG ulCPUCapInfo;
5942 ULONG ulReserved[19];
5944 ULONG ulGMCRestoreResetTime;
5945 ULONG ulMinimumNClk;
5946 ULONG ulIdleNClk;
5947 ULONG ulDDR_DLL_PowerUpTime;
5948 ULONG ulDDR_PLL_PowerUpTime;
5957 ULONG SclkDpmBoostMargin;
5958 ULONG SclkDpmThrottleMargin;
5961 ULONG ulBoostEngineCLock;
5976 ULONG ulLCDBitDepthControlVal;
5977 ULONG ulNbpStateMemclkFreq[4];
5980 ULONG ulNbpStateNClkFreq[4];
6151 ULONG ulBootUpEngineClock;
6152 ULONG ulDentistVCOFreq;
6153 ULONG ulBootUpUMAClock;
6155 ULONG ulBootUpReqDisplayVector;
6156 ULONG ulVBIOSMisc;
6157 ULONG ulGPUCapInfo;
6158 ULONG ulDISP_CLK2Freq;
6162 ULONG ulReserved2;
6163 ULONG ulSystemConfig;
6164 ULONG ulCPUCapInfo;
6165 ULONG ulReserved3;
6173 ULONG ulReserved[19];
6175 ULONG ulGMCRestoreResetTime;
6176 ULONG ulReserved4;
6177 ULONG ulIdleNClk;
6178 ULONG ulDDR_DLL_PowerUpTime;
6179 ULONG ulDDR_PLL_PowerUpTime;
6188 ULONG ulGPUReservedSysMemBaseAddrLo;
6189 ULONG ulGPUReservedSysMemBaseAddrHi;
6191 ULONG ulReserved5;
6203 ULONG ulLCDBitDepthControlVal;
6204 ULONG ulNbpStateMemclkFreq[4];
6205 ULONG ulPSPVersion;
6206 ULONG ulNbpStateNClkFreq[4];
6369 ULONG ulBootUpEngineClock;
6370 ULONG ulDentistVCOFreq;
6371 ULONG ulBootUpUMAClock;
6373 ULONG ulBootUpReqDisplayVector;
6374 ULONG ulVBIOSMisc;
6375 ULONG ulGPUCapInfo;
6376 ULONG ulDISP_CLK2Freq;
6380 ULONG ulReserved2;
6381 ULONG ulSystemConfig;
6382 ULONG ulCPUCapInfo;
6383 ULONG ulReserved3;
6394 ULONG ulReserved[2];
6397 ULONG ulGMCRestoreResetTime;
6398 ULONG ulReserved4;
6399 ULONG ulIdleNClk;
6400 ULONG ulDDR_DLL_PowerUpTime;
6401 ULONG ulDDR_PLL_PowerUpTime;
6410 ULONG ulGPUReservedSysMemBaseAddrLo;
6411 ULONG ulGPUReservedSysMemBaseAddrHi;
6412 ULONG ulReserved5[3];
6424 ULONG ulLCDBitDepthControlVal;
6425 ULONG ulNbpStateMemclkFreq[4]; // only 2 level is changed.
6426 ULONG ulPSPVersion;
6427 ULONG ulNbpStateNClkFreq[4];
6459 ULONG ucPara;
6482 ULONG ulVersionCode;
6486 ULONG ulCrcVal; // CRC
6492 ULONG ulBootUpEngineClock;
6493 ULONG ulDentistVCOFreq;
6494 ULONG ulBootUpUMAClock;
6495 ULONG ulReserved0[8];
6496 ULONG ulBootUpReqDisplayVector;
6497 ULONG ulVBIOSMisc;
6498 ULONG ulGPUCapInfo;
6499 ULONG ulReserved1;
6503 ULONG ulReserved2;
6504 ULONG ulSystemConfig;
6505 ULONG ulCPUCapInfo;
6506 ULONG ulReserved3;
6512 ULONG ulMsgReserved[10];
6514 ULONG ulReserved[7];
6516 ULONG ulReserved6[10];
6517 ULONG ulGMCRestoreResetTime;
6518 ULONG ulReserved4;
6519 ULONG ulIdleNClk;
6520 ULONG ulDDR_DLL_PowerUpTime;
6521 ULONG ulDDR_PLL_PowerUpTime;
6530 ULONG ulGPUReservedSysMemBaseAddrLo;
6531 ULONG ulGPUReservedSysMemBaseAddrHi;
6532 ULONG ulReserved5[3];
6544 ULONG ulLCDBitDepthControlVal;
6545 ULONG ulNbpStateMemclkFreq[2];
6546 ULONG ulReserved7[2];
6547 ULONG ulPSPVersion;
6548 ULONG ulNbpStateNClkFreq[4];
6555 ULONG ulReserved8[29];
6563 ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure
6570 ULONG ulPowerplayTable[192]; // Reserve 768 bytes space for PowerPlayInfoTable
6615 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz
6640 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
6671 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
7155 ULONG ulTargetMemoryClock; //In 10Khz unit
7193 ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position
7332 ULONG ulEfuseValue;
7429 ULONG ulDllResetClkRange;
7435 ULONG ucMemBlkId:8;
7436 ULONG ulMemClockRange:24;
7438 ULONG ulMemClockRange:24;
7439 ULONG ucMemBlkId:8;
7446 ULONG ulAccess;
7452 ULONG aulMemData[1];
7474 #define VALUE_DWORD SIZEOF ULONG
7492 ULONG ulARB_SEQDataBuf[32];
7501 ULONG ulRegValue;
7507 ULONG ulMCUcodeVersion;
7508 ULONG ulMCUcodeRomStartAddr;
7509 ULONG ulMCUcodeLength;
7567 ULONG ulSignature;
7585 ULONG ulReserved;
7607 ULONG ulReserved;
7608 ULONG ulFlags; // To enable/disable functionalities based on memory type
7609 ULONG ulEngineClock; // Override of default engine clock for particular memory type
7610 ULONG ulMemoryClock; // Override of default memory clock for particular memory type
7635 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
7671 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
7707 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
7744 ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock
7771 ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination
7793 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
7835 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
7867 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
7899 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP
7930 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP
7954 ULONG ulChannelMapCfg1; // channel mapping for channel8~15
7955 ULONG ulBankMapCfg;
7956 ULONG ulReserved;
7990 ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21]
8032 ULONG ulByte0BitRemapCh0;
8033 ULONG ulByte1BitRemapCh0;
8034 ULONG ulByte2BitRemapCh0;
8035 ULONG ulByte3BitRemapCh0;
8036 ULONG ulByte0BitRemapCh1;
8037 ULONG ulByte1BitRemapCh1;
8038 ULONG ulByte2BitRemapCh1;
8039 ULONG ulByte3BitRemapCh1;
8061 ULONG ulMCUcodeVersion;
8065 USHORT usMCUcodeOffset; //point of offset of MC uCode ULONG array.
8124 ULONG Ptr32_Bit;
8169 ULONG RsvdOffScrnMemSize;
8170 ULONG RsvdOffScrnMEmPtr;
8184 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function
8212 ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer
8213 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
8228 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode
8508 ULONG ulReserved;
8515 ULONG ulReserved;
8604 ULONG ulAnalogSetting[1];
8613 ULONG ulCondition;
8614 ULONG ulRegVal;
8618 ULONG ulCondition;
8620 ULONG ulRegVal;
8980 ULONG ulMiscInfo; //The power level should be arranged in ascending order
8981 ULONG ulReserved1; // must set to 0
8982 ULONG ulReserved2; // must set to 0
8996 ULONG ulMiscInfo; //The power level should be arranged in ascending order
8997 ULONG ulMiscInfo2;
8998 ULONG ulEngineClock;
8999 ULONG ulMemoryClock;
9011 ULONG ulMiscInfo; //The power level should be arranged in ascending order
9012 ULONG ulMiscInfo2;
9013 ULONG ulEngineClock;
9014 ULONG ulMemoryClock;
9232 ULONG Signature;
9233 ULONG TableLength; //Length
9238 ULONG OemRevision;
9239 ULONG CreatorId;
9240 ULONG CreatorRevision;
9259 ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
9260 ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
9261 ULONG Reserved[4]; //0x3C
9265 ULONG PCIBus; //0x4C
9266 ULONG PCIDevice; //0x50
9267 ULONG PCIFunction; //0x54
9272 ULONG Revision; //0x60
9273 ULONG ImageLength; //0x64
Indexes created Thu Oct 02 14:10:14 GMT 2025