Lines Matching defs:USHORT
54 #ifndef USHORT
55 typedef unsigned short USHORT;
212 USHORT usStructureSize;
226 USHORT usBiosRuntimeSegmentAddress;
227 USHORT usProtectedModeInfoOffset;
228 USHORT usConfigFilenameOffset;
229 USHORT usCRC_BlockOffset;
230 USHORT usBIOS_BootupMessageOffset;
231 USHORT usInt10Offset;
232 USHORT usPciBusDevInitCode;
233 USHORT usIoBaseAddress;
234 USHORT usSubsystemVendorID;
235 USHORT usSubsystemID;
236 USHORT usPCI_InfoOffset;
237 USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position
238 USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position
249 USHORT usBiosRuntimeSegmentAddress;
250 USHORT usProtectedModeInfoOffset;
251 USHORT usConfigFilenameOffset;
252 USHORT usCRC_BlockOffset;
253 USHORT usBIOS_BootupMessageOffset;
254 USHORT usInt10Offset;
255 USHORT usPciBusDevInitCode;
256 USHORT usIoBaseAddress;
257 USHORT usSubsystemVendorID;
258 USHORT usSubsystemID;
259 USHORT usPCI_InfoOffset;
260 USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position
261 USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position
275 USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1
276 USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON
277 USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
278 USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios
279 USHORT DIGxEncoderControl; //Only used by Bios
280 USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
281 USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1
282 USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed
283 USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2
284 USHORT GPIOPinControl; //Atomic Table, only used by Bios
285 USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1
286 USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1
287 USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2
288 USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
289 USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
290 USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
291 USHORT MemoryPLLInit; //Atomic Table, used only by Bios
292 USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes.
293 USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
294 USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios
295 USHORT SetUniphyInstance; //Atomic Table, only used by Bios
296 USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2
297 USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3
298 USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1
299 USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
300 USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
301 USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
302 USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead
303 USHORT GetConditionalGoldenSetting; //Only used by Bios
304 USHORT SMC_Init; //Function Table,directly used by various SW components,latest version 1.1
305 USHORT PatchMCSetting; //only used by BIOS
306 USHORT MC_SEQ_Control; //only used by BIOS
307 USHORT Gfx_Harvesting; //Atomic Table, Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting
308 USHORT EnableScaler; //Atomic Table, used only by Bios
309 USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
310 USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
311 USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1
312 USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1
313 USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios
314 USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1
315 USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1
316 USHORT GetSMUClockInfo; //Atomic Table, used only by Bios
317 USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1
318 USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios
319 USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios
320 USHORT LUT_AutoFill; //Atomic Table, only used by Bios
321 USHORT SetDCEClock; //Atomic Table, start from DCE11.1, shared by driver and VBIOS, change DISPCLK and DPREFCLK
322 USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1
323 USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1
324 USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1
325 USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1
326 USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
327 USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios
328 USHORT
329 USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios
330 USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components
331 USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components
332 USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init
333 USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1
334 USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
335 USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock
336 USHORT Gfx_Init; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock
337 USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios
338 USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
339 USHORT MemoryTraining; //Atomic Table, used only by Bios
340 USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2
341 USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
342 USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
343 USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
344 USHORT ReadEfuseValue; //Atomic Table, directly used by various SW components,latest version 1.1
345 USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"
346 USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
347 USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
348 USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender
349 USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
350 USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
351 USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
352 USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
353 USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios
354 USHORT DPEncoderService; //Function Table,only used by Bios
355 USHORT GetVoltageInfo; //Function Table,only used by Bios since SI
394 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
395 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
396 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
398 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
399 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
400 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
453 USHORT usFbDiv; //return Feedback value to be written to register
490 USHORT usFbDivFrac;
491 USHORT usFbDiv;
585 USHORT usSclk_fcw_frac; //fractional divider of fcw = usSclk_fcw_frac/65536
586 USHORT usSclk_fcw_int; //integer divider of fcwc
591 USHORT usSsc_fcw1_frac; //fcw1_frac when SSC enable
592 USHORT usSsc_fcw1_int; //fcw1_int when SSC enable
593 USHORT usReserved;
594 USHORT usPcc_fcw_int;
595 USHORT usSsc_fcw_slew_frac; //fcw_slew_frac when SSC enable
596 USHORT usPcc_fcw_slew_frac;
640 USHORT usMclk_fcw_frac; //fractional divider of fcw = usSclk_fcw_frac/65536
641 USHORT usMclk_fcw_int; //integer divider of fcwc
795 USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}
814 USHORT usPixelClock; // in 10KHz; for bios convenient
830 USHORT usPixelClock; // in 10KHz; for bios convenient
908 USHORT usPixelClock; // in 10KHz; for bios convenient
989 USHORT usPixelClock; // in 10KHz; for bios convenient
1045 USHORT usPixelClock; // in 10KHz; for bios convenient
1160 USHORT usPixelClock; // in 10KHz; for bios convenient
1161 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1288 USHORT usPixelClock; // in 10KHz; for bios convenient
1289 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1327 USHORT usPixelClock; // in 10KHz; for bios convenient
1328 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1422 USHORT usPixelClock; // in 10KHz; for bios convenient
1423 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1481 USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio
1615 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
1616 USHORT usConnectorId; // connector id, valid when ucAction = INIT
1708 USHORT usPwmFreq; // in unit of Hz, 200 means 200Hz
1720 USHORT usBlackColorRCr;
1721 USHORT usBlackColorGY;
1722 USHORT usBlackColorBCb;
1744 USHORT usOverscanRight; // right
1745 USHORT usOverscanLeft; // left
1746 USHORT usOverscanBottom; // bottom
1747 USHORT usOverscanTop; // top
1821 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1823 USHORT usRefDiv; // Reference divider
1824 USHORT usFbDiv; // feedback divider
1841 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1843 USHORT usRefDiv; // Reference divider
1844 USHORT usFbDiv; // feedback divider
1888 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1890 USHORT usRefDiv; // Reference divider
1891 USHORT usFbDiv; // feedback divider
1918 USHORT usPixelClock; // target the pixel clock to drive the CRTC timing
1920 USHORT usFbDiv; // feedback divider integer part.
1968 USHORT usFbDiv; // feedback divider integer part.
2118 USHORT usPixelClock;
2134 USHORT usPixelClock; // target pixel clock
2208 USHORT usPrescale; //Ratio between Engine clock and I2C clock
2209 USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID
2210 USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status
2226 USHORT usPrescale; //Ratio between Engine clock and I2C clock
2227 USHORT usByteOffset; //Write to which byte
2244 USHORT usPrescale; //Ratio between Engine clock and I2C clock
2260 USHORT usPwrBudget; //how much power currently boot to in unit of watt
2267 USHORT usPwrBudget; //how much power currently boot to in unit of watt
2279 USHORT usSpreadSpectrumPercentage;
2289 USHORT usSpreadSpectrumPercentage;
2301 USHORT usSpreadSpectrumPercentage;
2312 USHORT usSpreadSpectrumPercentage;
2318 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
2319 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC
2337 USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0
2343 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
2344 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC
2385 USHORT usMemTrainingMode;
2386 USHORT usReserved;
2404 USHORT usPixelClock; // in 10KHz; for bios convenient
2424 USHORT usPixelClock; // in 10KHz; for bios convenient
2514 USHORT usPixelClock;
2523 USHORT usPixelClock;
2610 USHORT usVoltageLevel; // real voltage level
2618 USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. )
2674 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
2688 USHORT usVoltageLevel;
2689 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator
2713 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
2723 USHORT usVoltageLevel; // real voltage level in unit of mv
2724 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator
2725 USHORT usTDP_Current; // TDP_Current in unit of 0.01A
2726 USHORT usTDP_Power; // TDP_Current in unit of 0.1W
2735 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
2767 USHORT usPixelClock; // in 10KHz; for bios convenient
2787 USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position!
2788 USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios
2789 USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios
2790 USHORT StandardVESA_Timing; // Only used by Bios
2791 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4
2792 USHORT PaletteData; // Only used by BIOS
2793 USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info
2794 USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1
2795 USHORT SMU_Info; // Shared by various SW components,latest version 1.1
2796 USHORT SupportedDevicesInfo; // Will be obsolete from R600
2797 USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600
2798 USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600
2799 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1
2800 USHORT VESA_ToInternalModeLUT; // Only used by Bios
2801 USHORT GFX_Info; // Shared by various SW components,latest version 2.1 will be used from R600
2802 USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600
2803 USHORT GPUVirtualizationInfo; // Will be obsolete from R600
2804 USHORT SaveRestoreInfo; // Only used by Bios
2805 USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
2806 USHORT OemInfo; // Defined and used by external SW, should be obsolete soon
2807 USHORT XTMDS_Info; // Will be obsolete from R600
2808 USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
2809 USHORT Object_Header; // Shared by various SW components,latest version 1.1
2810 USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!!
2811 USHORT MC_InitParameter; // Only used by command table
2812 USHORT ASIC_VDDC_Info; // Will be obsolete from R600
2813 USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info"
2814 USHORT TV_VideoMode; // Only used by command table
2815 USHORT VRAM_Info; // Only used by command table, latest version 1.3
2816 USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1
2817 USHORT IntegratedSystemInfo; // Shared by various SW components
2818 USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
2819 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1
2820 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1
2821 USHORT ServiceInfo;
2905 USHORT Reserved:1;
2906 USHORT SCL2Redefined:1;
2907 USHORT PostWithoutModeSet:1;
2908 USHORT HyperMemory_Size:4;
2909 USHORT HyperMemory_Support:1;
2910 USHORT PPMode_Assigned:1;
2911 USHORT WMI_SUPPORT:1;
2912 USHORT GPUControlsBL:1;
2913 USHORT EngineClockSS_Support:1;
2914 USHORT MemoryClockSS_Support:1;
2915 USHORT ExtendedDesktopSupport:1;
2916 USHORT DualCRTC_Support:1;
2917 USHORT FirmwarePosted:1;
2919 USHORT FirmwarePosted:1;
2920 USHORT DualCRTC_Support:1;
2921 USHORT ExtendedDesktopSupport:1;
2922 USHORT MemoryClockSS_Support:1;
2923 USHORT EngineClockSS_Support:1;
2924 USHORT GPUControlsBL:1;
2925 USHORT WMI_SUPPORT:1;
2926 USHORT PPMode_Assigned:1;
2927 USHORT HyperMemory_Support:1;
2928 USHORT HyperMemory_Size:4;
2929 USHORT PostWithoutModeSet:1;
2930 USHORT SCL2Redefined:1;
2931 USHORT Reserved:1;
2938 USHORT susAccess;
2945 USHORT susAccess;
2966 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2967 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2968 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2969 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2970 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2971 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2972 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2973 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2974 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2975 USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!!
2977 USHORT usReferenceClock; //In 10Khz unit
2978 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
3002 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
3003 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
3004 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
3005 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
3006 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
3007 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
3008 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
3009 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3010 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3011 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
3013 USHORT usReferenceClock; //In 10Khz unit
3014 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
3039 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
3040 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
3041 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
3042 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
3043 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
3044 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
3045 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
3046 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3047 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3048 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
3050 USHORT usReferenceClock; //In 10Khz unit
3051 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
3072 USHORT usBootUpVDDCVoltage; //In MV unit
3073 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
3074 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
3077 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
3078 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
3079 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
3080 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
3081 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
3082 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
3083 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
3084 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3085 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3086 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
3088 USHORT usReferenceClock; //In 10Khz unit
3089 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
3111 USHORT usBootUpVDDCVoltage; //In MV unit
3112 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
3113 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
3116 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
3117 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
3118 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
3119 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
3120 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
3121 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
3122 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
3123 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3124 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3125 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
3127 USHORT usCoreReferenceClock; //In 10Khz unit
3128 USHORT usMemoryReferenceClock; //In 10Khz unit
3129 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
3161 USHORT usBootUpVDDCVoltage; //In MV unit
3162 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
3163 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
3170 USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC
3171 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3172 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3173 USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output;
3175 USHORT usCoreReferenceClock; //In 10Khz unit
3176 USHORT usMemoryReferenceClock; //In 10Khz unit
3177 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
3182 USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output;
3183 USHORT usBootUpVDDGFXVoltage; //In unit of mv;
3211 USHORT usReserved1;
3212 USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage
3213 USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage
3216 USHORT usFSBClock; //In MHz unit
3217 USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable
3220 USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal
3221 USHORT usK8MemoryClock; //in MHz unit
3222 USHORT usK8SyncStartDelay; //in 0.01 us unit
3223 USHORT usK8DataReturnTime; //in 0.01 us unit
3294 USHORT usNumberOfCyclesInPeriod;
3295 USHORT usMaxNBVoltage;
3296 USHORT usMinNBVoltage;
3297 USHORT usBootUpNBVoltage;
3299 USHORT usMinHTLinkWidth;
3300 USHORT usMaxHTLinkWidth;
3301 USHORT usUMASyncStartDelay;
3302 USHORT usUMADataReturnTime;
3303 USHORT usLinkStatusZeroTime;
3304 USHORT usDACEfuse; //for storing badgap value (for RS880 only)
3307 USHORT usMaxUpStreamHTLinkWidth;
3308 USHORT usMaxDownStreamHTLinkWidth;
3309 USHORT usMinUpStreamHTLinkWidth;
3310 USHORT usMinDownStreamHTLinkWidth;
3311 USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW.
3312 USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
3461 USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
3462 USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
3463 USHORT usBootUpNBVoltage; //boot up NB voltage
3474 USHORT usReserved;
3685 USHORT usClkMaskRegisterIndex;
3686 USHORT usClkEnRegisterIndex;
3687 USHORT usClkY_RegisterIndex;
3688 USHORT usClkA_RegisterIndex;
3689 USHORT usDataMaskRegisterIndex;
3690 USHORT usDataEnRegisterIndex;
3691 USHORT usDataY_RegisterIndex;
3692 USHORT usDataA_RegisterIndex;
3722 USHORT Reserved:6;
3723 USHORT RGB888:1;
3724 USHORT DoubleClock:1;
3725 USHORT Interlace:1;
3726 USHORT
3727 USHORT V_ReplicationBy2:1;
3728 USHORT H_ReplicationBy2:1;
3729 USHORT VerticalCutOff:1;
3730 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
3731 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
3732 USHORT HorizontalCutOff:1;
3734 USHORT HorizontalCutOff:1;
3735 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
3736 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
3737 USHORT VerticalCutOff:1;
3738 USHORT H_ReplicationBy2:1;
3739 USHORT V_ReplicationBy2:1;
3740 USHORT CompositeSync:1;
3741 USHORT Interlace:1;
3742 USHORT DoubleClock:1;
3743 USHORT RGB888:1;
3744 USHORT Reserved:6;
3751 USHORT usAccess;
3758 USHORT usAccess;
3803 USHORT usH_Size;
3804 USHORT usH_Blanking_Time;
3805 USHORT usV_Size;
3806 USHORT usV_Blanking_Time;
3807 USHORT usH_SyncOffset;
3808 USHORT usH_SyncWidth;
3809 USHORT usV_SyncOffset;
3810 USHORT usV_SyncWidth;
3823 USHORT usH_Total; // horizontal total
3824 USHORT usH_Disp; // horizontal display
3825 USHORT usH_SyncStart; // horozontal Sync start
3826 USHORT usH_SyncWidth; // horizontal Sync width
3827 USHORT usV_Total; // vertical total
3828 USHORT usV_Disp; // vertical display
3829 USHORT usV_SyncStart; // vertical Sync start
3830 USHORT usV_SyncWidth; // vertical Sync width
3849 USHORT usCRTC_H_Total;
3850 USHORT usCRTC_H_Disp;
3851 USHORT usCRTC_H_SyncStart;
3852 USHORT usCRTC_H_SyncWidth;
3853 USHORT usCRTC_V_Total;
3854 USHORT usCRTC_V_Disp;
3855 USHORT usCRTC_V_SyncStart;
3856 USHORT usCRTC_V_SyncWidth;
3857 USHORT usPixelClock; //in 10Khz unit
3859 USHORT usCRTC_OverscanRight;
3860 USHORT usCRTC_OverscanLeft;
3861 USHORT usCRTC_OverscanBottom;
3862 USHORT usCRTC_OverscanTop;
3863 USHORT usReserve;
3870 USHORT usPixClk;
3871 USHORT usHActive;
3872 USHORT usHBlanking_Time;
3873 USHORT usVActive;
3874 USHORT usVBlanking_Time;
3875 USHORT usHSyncOffset;
3876 USHORT usHSyncWidth;
3877 USHORT usVSyncOffset;
3878 USHORT usVSyncWidth;
3879 USHORT usImageHSize;
3880 USHORT usImageVSize;
3904 USHORT usModePatchTableOffset;
3905 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
3906 USHORT usOffDelayInMs;
3924 USHORT usExtInfoTableOffset;
3925 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
3926 USHORT usOffDelayInMs;
3936 USHORT usLCDVenderID;
3937 USHORT usLCDProductID;
3994 USHORT usExtInfoTableOffset;
3997 USHORT usSupportedRefreshRate;
4010 USHORT usLCDVenderID;
4011 USHORT usLCDProductID;
4018 USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13
4035 USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode.
4085 USHORT usHDisp;
4086 USHORT usVDisp;
4100 USHORT usLCDCap;
4118 USHORT usHSize;
4119 USHORT usVSize;
4136 USHORT usSpreadSpectrumPercentage;
4336 USHORT usFirmwareUseInKb;
4337 USHORT usReserved;
4350 USHORT usFirmwareUseInKb;
4351 USHORT usFBUsedByDrvInKb;
4365 USHORT usGpioPin_AIndex;
4407 USHORT usAOffset;
4447 USHORT usMask_PinRegisterIndex;
4448 USHORT usEN_PinRegisterIndex;
4449 USHORT usY_PinRegisterIndex;
4450 USHORT usA_PinRegisterIndex;
4491 USHORT usDeviceSupport;
4492 USHORT usConnectorObjectTableOffset;
4493 USHORT usRouterObjectTableOffset;
4494 USHORT usEncoderObjectTableOffset;
4495 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent.
4496 USHORT usDisplayPathTableOffset;
4502 USHORT usDeviceSupport;
4503 USHORT usConnectorObjectTableOffset;
4504 USHORT usRouterObjectTableOffset;
4505 USHORT usEncoderObjectTableOffset;
4506 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent.
4507 USHORT usDisplayPathTableOffset;
4508 USHORT usMiscObjectTableOffset;
4514 USHORT usDeviceTag; //supported device
4515 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH
4516 USHORT usConnObjectId; //Connector Object ID
4517 USHORT usGPUObjectId; //GPU ID
4518 USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector.
4523 USHORT usDeviceTag; //supported device
4524 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH
4525 USHORT usConnObjectId; //Connector Object ID
4526 USHORT usGPUObjectId; //GPU ID
4527 USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder
4540 USHORT usObjectID;
4541 USHORT usSrcDstTableOffset;
4542 USHORT usRecordOffset; //this pointing to a bunch of records defined below
4543 USHORT usReserved;
4556 USHORT usSrcObjectID[1];
4558 USHORT usDstObjectID[1];
4627 USHORT usDeviceTag; //A bit vector to show what devices are supported
4628 USHORT usDeviceACPIEnum; //16bit device ACPI id.
4629 USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions
4632 USHORT usExtEncoderObjId; //external encoder object id
4639 USHORT usCaps;
4640 USHORT usReserved;
4729 USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT"
4730 USHORT usPadding;
4843 USHORT usEncoderCap;
4846 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future
4847 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4848 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
4850 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
4851 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4852 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future
4863 USHORT usEncoderCap;
4866 USHORT usReserved:12; // Bit4-15 may be defined for other capability in future
4867 USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable
4868 USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used starting from CZ( APU) Ellemere (dGPU)
4869 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4870 USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable
4872 USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable
4873 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4874 USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used starting from CZ( APU) Ellemere (dGPU)
4875 USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable
4876 USHORT usReserved:12; // Bit4-15 may be defined for other capability in future
4890 USHORT usMaxPixClk;
4946 USHORT usObjectID; //could be connector, encorder or other object in object.h
4952 USHORT usReserved;
4967 USHORT usConnectorObjectId;
4996 USHORT usVDDCBaseLevel; //In number of 50mv unit
4997 USHORT usReserved; //For possible extension table offset
5017 USHORT usVoltageBaseLevel; // In number of 1mv unit
5018 USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit
5028 USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code
5029 USHORT usVoltageValue; // The corresponding Voltage Value, in mV
5045 USHORT usGpioPin_AIndex; //GPIO_PAD register index
5109 USHORT usVoltage;
5115 USHORT usSize; //Size of Object
5131 USHORT usVoltageValue; // The corresponding Voltage Value, in mV
5136 USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register
5137 USHORT usVoltageId;
5138 USHORT usLeakageId; // The corresponding Voltage Value, in mV
5188 USHORT usLoadLine_PSI;
5208 USHORT usVAdjOffset; // Adjust Voltage offset in unit of mv
5240 USHORT usSize;
5241 USHORT usEfuseSpareStartAddr;
5242 USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id,
5261 USHORT usLeakageBinArrayOffset; // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher)
5264 USHORT usElbVDDC_IdArrayOffset; // offset of USHORT virtual VDDC voltage id ( 0xff01~0xff08 )
5265 USHORT usElbVDDC_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array
5268 USHORT usElbVDDCI_IdArrayOffset; // offset of USHORT virtual VDDCI voltage id ( 0xff01~0xff08 )
5269 USHORT usElbVDDCI_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array
5277 USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112
5287 USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112
5311 USHORT usLkgEuseIndex;
5318 USHORT usPowerDpm0;
5319 USHORT usCurrentDpm0;
5320 USHORT usPowerDpm1;
5321 USHORT usCurrentDpm1;
5322 USHORT usPowerDpm2;
5323 USHORT usCurrentDpm2;
5324 USHORT usPowerDpm3;
5325 USHORT usCurrentDpm3;
5326 USHORT usPowerDpm4;
5327 USHORT usCurrentDpm4;
5328 USHORT usPowerDpm5;
5329 USHORT usCurrentDpm5;
5330 USHORT usPowerDpm6;
5331 USHORT usCurrentDpm6;
5332 USHORT usPowerDpm7;
5333 USHORT usCurrentDpm7;
5352 USHORT usLkgEuseIndex;
5359 USHORT usPowerDpm0;
5360 USHORT usPowerDpm1;
5361 USHORT usPowerDpm2;
5362 USHORT usPowerDpm3;
5363 USHORT usPowerDpm4;
5364 USHORT usPowerDpm5;
5365 USHORT usPowerDpm6;
5366 USHORT usPowerDpm7;
5394 USHORT usLkgEuseIndex;
5403 USHORT usPowerDpm0;
5404 USHORT usParamNegFlag; //bit0 =1 :indicate ulRoBeta is Negative, bit1=1 indicate Kv_m max is postive
5406 USHORT usPowerDpm1;
5407 USHORT usPowerDpm2;
5408 USHORT usPowerDpm3;
5409 USHORT usPowerDpm4;
5410 USHORT usPowerDpm5;
5411 USHORT usPowerDpm6;
5412 USHORT usPowerDpm7;
5453 USHORT usLkgEuseIndex;
5460 USHORT usPowerDpm0;
5461 USHORT usPowerDpm1;
5462 USHORT usPowerDpm2;
5463 USHORT usPowerDpm3;
5464 USHORT usPowerDpm4;
5465 USHORT usPowerDpm5;
5466 USHORT usPowerDpm6;
5467 USHORT usPowerDpm7;
5479 USHORT usParamNegFlag;
5480 USHORT usSpeed_Model;
5515 USHORT usLkgEuseIndex; //Efuse Lkg_FT address ( BYTE address )
5559 USHORT usLkgEuseIndex;
5600 USHORT usAVFS_meanNsigma_DC_tol_sigma;
5601 USHORT usAVFS_meanNsigma_Platform_mean;
5602 USHORT usAVFS_meanNsigma_Platform_sigma;
5610 USHORT usAVFSGB_FUSE_TABLE_CKSOFF_m2;
5613 USHORT usAVFSGB_FUSE_TABLE_CKSON_m2;
5615 USHORT usMaxVoltage_0_25mv;
5620 USHORT usPSM_Age_ComFactor;
5630 USHORT ucFcw_pcc;
5631 USHORT ucFcw_trans_upper;
5632 USHORT ucRcw_trans_lower;
5671 USHORT usSensPwr; // in unit of watt
5703 USHORT usVoltageLevel; // The real Voltage Level round up value in unit of mv,
5710 USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK
5711 USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK
5729 USHORT usRequestedPWMFreqInHz;
5735 USHORT usNBP0Voltage;
5736 USHORT usNBP1Voltage;
5737 USHORT usBootUpNBVoltage;
5738 USHORT usExtDispConnInfoOffset;
5739 USHORT usPanelRefreshRateRange;
5751 USHORT usPCIEClkSSPercentage;
5752 USHORT usPCIEClkSSType;
5753 USHORT usLvdsSSPercentage;
5754 USHORT usLvdsSSpreadRateIn10Hz;
5755 USHORT usHDMISSPercentage;
5756 USHORT usHDMISSpreadRateIn10Hz;
5757 USHORT usDVISSPercentage;
5758 USHORT usDVISSpreadRateIn10Hz;
5761 USHORT SclkDpmTdpLimitPG;
5762 USHORT SclkDpmTdpLimitBoost;
5766 USHORT GnbTdpLimit;
5767 USHORT usMaxLVDSPclkFreqInSingleLink;
5927 USHORT usRequestedPWMFreqInHz;
5933 USHORT usNBP0Voltage;
5934 USHORT usNBP1Voltage;
5935 USHORT usBootUpNBVoltage;
5936 USHORT usExtDispConnInfoOffset;
5937 USHORT usPanelRefreshRateRange;
5949 USHORT usPCIEClkSSPercentage;
5950 USHORT usPCIEClkSSType;
5951 USHORT usLvdsSSPercentage;
5952 USHORT usLvdsSSpreadRateIn10Hz;
5953 USHORT usHDMISSPercentage;
5954 USHORT usHDMISSpreadRateIn10Hz;
5955 USHORT usDVISSPercentage;
5956 USHORT usDVISSpreadRateIn10Hz;
5959 USHORT SclkDpmTdpLimitPG;
5960 USHORT SclkDpmTdpLimitBoost;
5964 USHORT GnbTdpLimit;
5965 USHORT usMaxLVDSPclkFreqInSingleLink;
5978 USHORT usNBP2Voltage;
5979 USHORT usNBP3Voltage;
6159 USHORT usRequestedPWMFreqInHz;
6166 USHORT usGPUReservedSysMemSize;
6167 USHORT usExtDispConnInfoOffset;
6168 USHORT usPanelRefreshRateRange;
6180 USHORT usPCIEClkSSPercentage;
6181 USHORT usPCIEClkSSType;
6182 USHORT usLvdsSSPercentage;
6183 USHORT usLvdsSSpreadRateIn10Hz;
6184 USHORT usHDMISSPercentage;
6185 USHORT usHDMISSpreadRateIn10Hz;
6186 USHORT usDVISSPercentage;
6187 USHORT usDVISSpreadRateIn10Hz;
6192 USHORT usMaxLVDSPclkFreqInSingleLink;
6207 USHORT usNBPStateVoltage[4];
6208 USHORT usBootUpNBVoltage;
6209 USHORT usReserved2;
6377 USHORT usRequestedPWMFreqInHz;
6384 USHORT usGPUReservedSysMemSize;
6385 USHORT usExtDispConnInfoOffset;
6386 USHORT usPanelRefreshRateRange;
6402 USHORT usPCIEClkSSPercentage;
6403 USHORT usPCIEClkSSType;
6404 USHORT usLvdsSSPercentage;
6405 USHORT usLvdsSSpreadRateIn10Hz;
6406 USHORT usHDMISSPercentage;
6407 USHORT usHDMISSpreadRateIn10Hz;
6408 USHORT usDVISSPercentage;
6409 USHORT usDVISSpreadRateIn10Hz;
6413 USHORT usMaxLVDSPclkFreqInSingleLink;
6428 USHORT usNBPStateVoltage[4];
6429 USHORT usBootUpNBVoltage;
6464 USHORT usPara[3];
6500 USHORT usRequestedPWMFreqInHz;
6507 USHORT usGPUReservedSysMemSize;
6508 USHORT usExtDispConnInfoOffset;
6509 USHORT usPanelRefreshRateRange;
6522 USHORT usPCIEClkSSPercentage;
6523 USHORT usPCIEClkSSType;
6524 USHORT usLvdsSSPercentage;
6525 USHORT usLvdsSSpreadRateIn10Hz;
6526 USHORT usHDMISSPercentage;
6527 USHORT usHDMISSpreadRateIn10Hz;
6528 USHORT usDVISSPercentage;
6529 USHORT usDVISSpreadRateIn10Hz;
6533 USHORT usMaxLVDSPclkFreqInSingleLink;
6549 USHORT usNBPStateVoltage[4];
6550 USHORT usBootUpNBVoltage;
6616 USHORT usSpreadSpectrumPercentage; //in unit of 0.01%
6617 USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq
6642 USHORT usSpreadSpectrumPercentage; //in unit of 0.01%
6643 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq
6673 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% or 0.001%, decided by ucSpreadSpectrumMode bit4
6674 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq
7130 #define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT))
7135 #define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT))
7208 USHORT usHight; // Image Hight
7209 USHORT usWidth; // Image Width
7216 USHORT usHight; // Image Hight
7217 USHORT usWidth; // Image Width
7225 USHORT usHight; // Image Hight
7226 USHORT usWidth; // Image Width
7229 USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0.
7234 USHORT usHight; // Image Hight
7235 USHORT usWidth; // Image Width
7236 USHORT usGraphPitch;
7257 USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address
7258 USHORT usMemorySize; //8Kb blocks aligned
7265 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC
7266 USHORT usY_Size;
7272 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC
7273 USHORT usSurface;
7275 USHORT usY_Size;
7276 USHORT usDispXStart;
7277 USHORT usDispYStart;
7285 USHORT usLutStartIndex;
7286 USHORT usLutLength;
7287 USHORT usLutOffsetInVram;
7323 USHORT usEfuseIndex;
7381 USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table
7382 USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table
7383 USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table
7384 USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table
7385 USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table
7391 USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients
7392 USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients
7405 USHORT usSTD_HDisp;
7406 USHORT usSTD_VDisp;
7407 USHORT usSTD_RefreshRate;
7408 USHORT usReserved;
7413 USHORT usVESA_ModeNumber;
7414 USHORT usExtendedModeNumber;
7457 USHORT usRegIndex; // MC register index
7463 USHORT usRegIndexTblSize; //size of asRegIndexBuf
7464 USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK
7488 USHORT usAdjustARB_SEQDataOffset;
7489 USHORT usMCInitMemTypeTblOffset;
7490 USHORT usMCInitCommonTblOffset;
7491 USHORT usMCInitPowerDownTblOffset;
7500 USHORT usRegIndex;
7510 USHORT usMcRegInitTableOffset; // offset of ATOM_REG_INIT_SETTING array for MC core register settings.
7511 USHORT usReserved; // offset of ATOM_INIT_REG_BLOCK for MC SEQ/PHY register setting
7572 USHORT usParametersLength;
7573 USHORT usUCodeLength;
7574 USHORT usReserved1;
7575 USHORT usReserved2;
7586 USHORT usEMRSValue;
7587 USHORT usMRSValue;
7588 USHORT usReserved;
7611 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
7612 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
7613 USHORT usEMRSValue;
7614 USHORT usMRSValue;
7615 USHORT usReserved;
7637 USHORT usMRS; // mode register
7638 USHORT usDDR3_MR0;
7641 USHORT usEMRS; // extended mode register
7642 USHORT usDDR3_MR1;
7664 USHORT usDDR3_MR2;
7672 USHORT usMRS; // mode register
7673 USHORT usEMRS; // extended mode register
7708 USHORT usMRS; // mode register
7709 USHORT usEMRS; // extended mode register
7746 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
7747 USHORT usDDR3_Reserved; // Not used for DDR3 memory
7750 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
7751 USHORT usDDR3_MR3; // Used for DDR3 memory
7772 USHORT usSize; // size of ATOM_VRAM_MODULE_V3
7773 USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage
7774 USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage
7794 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
7795 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7797 USHORT usReserved;
7814 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
7815 USHORT usDDR3_Reserved;
7818 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
7819 USHORT usDDR3_MR3; // Used for DDR3 memory
7836 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
7837 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7839 USHORT usReserved;
7855 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
7856 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
7868 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
7869 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7871 USHORT usReserved;
7887 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
7888 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
7900 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7
7901 USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
7902 USHORT usEnableChannels; // bit vector which indicate which channels are enabled
7914 USHORT usSEQSettingOffset;
7917 USHORT usEMRS2Value; // EMRS2/MR2 Value.
7918 USHORT usEMRS3Value; // EMRS3/MR3 Value.
7931 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7
7932 USHORT usMcRamCfg; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
7933 USHORT usEnableChannels; // bit vector which indicate which channels are enabled
7942 USHORT usReserved; // Not used
7943 USHORT usMemorySize; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
7947 USHORT usEMRS2Value; // EMRS2/MR2 Value.
7948 USHORT usEMRS3Value; // EMRS3/MR3 Value.
7971 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
7972 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
7973 USHORT usRerseved;
7986 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
7987 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
7988 USHORT usRerseved;
8000 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
8001 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
8002 USHORT usPerBytePresetOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings
8003 USHORT usReserved[3];
8014 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
8015 USHORT
8016 USHORT usMcAdjustPerTileTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings
8017 USHORT usMcPhyInitTableOffset; // offset of ATOM_INIT_REG_BLOCK structure for MC phy init set
8018 USHORT usDramDataRemapTblOffset; // offset of ATOM_DRAM_DATA_REMAP array to indicate DRAM data lane to GPU mapping
8019 USHORT usReserved1;
8062 USHORT usMCIOInitLen; //len of ATOM_REG_INIT_SETTING array
8063 USHORT usMCUcodeLen; //len of ATOM_MC_UCODE_DATA array
8064 USHORT usMCIORegInitOffset; //point of offset of ATOM_REG_INIT_SETTING array
8065 USHORT usMCUcodeOffset; //point of offset of MC uCode ULONG array.
8081 USHORT GPIO_Info;
8117 USHORT Offset16;
8118 USHORT Segment16;
8130 USHORT VbeVersion;
8134 USHORT TotalMemory;
8141 USHORT OemSoftRev;
8162 USHORT HSize;
8163 USHORT VSize;
8164 USHORT FPType;
8177 USHORT ModeAttributes; // dw ? ; mode attributes
8180 USHORT WinGranularity; // dw ? ; window granularity
8181 USHORT WinSize; // dw ? ; window size
8182 USHORT WinASegment; // dw ? ; window A start segment
8183 USHORT WinBSegment; // dw ? ; window B start segment
8185 USHORT BytesPerScanLine;// dw ? ; bytes per scan line
8188 USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters
8189 USHORT YResolution; // dw ? ; vertical resolution in pixels or characters
8214 USHORT Reserved_2; // dw 0 ; reserved - always set to 0
8217 USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes
8283 USHORT usTransmitterObjId;
8284 USHORT usSupportDevice;
8307 USHORT usEncoderCmdTblId;
8313 USHORT ptrTransmitterInfo;
8314 USHORT ptrEncoderInfo;
8323 USHORT ptrTransmitterInfo;
8324 USHORT ptrEncoderInfo;
8325 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary.
8344 USHORT usTransmitterObjId;
8345 USHORT usDispClkIdOffset; // point to clock source id list supported by Encoder Object
8357 USHORT ptrTransmitterInfo;
8358 USHORT ptrEncoderInfo;
8359 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary.
8360 USHORT usReserved;
8385 USHORT asDevicePriority[16];
8391 USHORT lpAuxRequest;
8392 USHORT lpDataOut;
8406 USHORT lpAuxRequest;
8407 USHORT lpDataOut;
8424 USHORT ucLinkClock;
8444 USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
8487 USHORT lpI2CDataOut;
8557 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
8558 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
8559 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
8560 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info
8561 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
8566 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
8567 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
8568 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
8569 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info
8570 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
8571 USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info
8572 USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings
8578 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
8579 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
8580 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
8581 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info
8582 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
8583 USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info
8584 USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings
8585 USHORT usEDPVsLegacyModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Legacy Mode Voltage Swing and Pre-Emphasis for each Link clock
8586 USHORT useDPVsLowVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Low VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock
8587 USHORT useDPVsHighVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP High VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock
8588 USHORT useDPVsStretchModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Stretch Mode Voltage Swing and Pre-Emphasis for each Link clock
8589 USHORT useDPVsSingleVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vdiff Mode Voltage Swing and Pre-Emphasis for each Link clock
8590 USHORT useDPVsVariablePremModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vidff+Variable PreEmphasis Voltage Swing and Pre-Emphasis for each Link clock
8595 USHORT usRegisterIndex;
8601 USHORT usMaxClockFreq;
8608 USHORT usEntrySize;
8624 USHORT usRegIndex;
8625 USHORT usSize;
8630 USHORT usRegIndex;
8631 USHORT usSize;
8638 USHORT usSize;
8645 USHORT usSize;
8667 USHORT usLabelCoreMainInitBIOS;
8669 USHORT usPciDataStructureOffset;
8675 USHORT usLabelCoreVPOSTNoMode;
8676 USHORT usSpecialPostOffset;
8679 USHORT usROM_HeaderInformationTableOffset;
8683 USHORT usCoreXFuncFarHandlerOffset;
8686 USHORT usCoreVFuncFarHandlerOffset;
8688 USHORT usATOM_BIOS_MESSAGE_Offset;
8721 USHORT usMaxFrequency; // in 10kHz unit
8722 USHORT usReserved;
8733 USHORT usDAC1_FORCE_Data;
8737 USHORT usDAC2_CRT2_FORCE_Data;
8738 USHORT usDAC2_CRT2_MUX_RegisterIndex;
8742 USHORT usDAC2_TV1_FORCE_Data;
8743 USHORT usDAC2_TV1_MUX_RegisterIndex;
8747 USHORT usDAC2_CV_FORCE_Data;
8748 USHORT usDAC2_CV_MUX_RegisterIndex;
8752 USHORT usDAC2_TV2_FORCE_Data;
8806 USHORT usDeviceSupport;
8820 USHORT usDeviceSupport;
8828 USHORT
8839 USHORT usFrequency;
8852 USHORT usMaxFrequency; // in 10Khz
8878 USHORT usPixelClock;
8879 USHORT usEncoderID;
8903 USHORT usSingleLinkMaxFrequency;
8983 USHORT usEngineClock;
8984 USHORT usMemoryClock;
9199 USHORT usOffset; // offset of the hole ( from the start of the binary )
9200 USHORT usLength; // length of the hole ( in bytes )
9209 USHORT usSigOffset; // Signature offset ( from the start of the binary )
9210 USHORT usSigLength; // Signature length
9268 USHORT VendorID; //0x58
9269 USHORT DeviceID; //0x5A
9270 USHORT SSVID; //0x5C
9271 USHORT SSID; //0x5E
Indexes created Thu Oct 02 14:10:14 GMT 2025