Lines Matching defs:ucflag
2056 ULONG ulDISPClkFreq; // target DISPCLK frquency in unit of 10kHz, return real DISPCLK frequency. when ucFlag[1]=1, in unit of 100Hz.
2057 UCHAR ucFlag; // bit0=1: DPREFCLK bypass DFS bit0=0: DPREFCLK not bypass DFS
2058 UCHAR ucCrtc; // use when enable DCCG pixel clock ucFlag[1]=1
2059 UCHAR ucPpllId; // use when enable DCCG pixel clock ucFlag[1]=1
2060 UCHAR ucDeepColorRatio; // use when enable DCCG pixel clock ucFlag[1]=1
2070 //SET_DCE_CLOCK_PARAMETERS_V1_1.ucFlag
5020 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv
7661 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
7688 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
7724 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
7780 UCHAR ucFlag; // To enable/disable functionalities based on memory type
7803 UCHAR ucFlag; // To enable/disable functionalities based on memory type
7845 UCHAR ucFlag; // To enable/disable functionalities based on memory type
7877 UCHAR ucFlag; // To enable/disable functionalities based on memory type
8488 UCHAR ucFlag;
8496 //ucFlag
Indexes created Thu Oct 02 14:10:14 GMT 2025