Lines Matching defs:ast
18 struct ast_private *ast = dev->dev_private;
20 return request_firmware(&ast->dp501_fw, "ast_dp501_fw.bin", dev->dev);
23 static void send_ack(struct ast_private *ast)
26 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
28 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
31 static void send_nack(struct ast_private *ast)
34 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
36 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
39 static bool wait_ack(struct ast_private *ast)
44 waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
55 static bool wait_nack(struct ast_private *ast)
60 waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
71 static void set_cmd_trigger(struct ast_private *ast)
73 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x40);
76 static void clear_cmd_trigger(struct ast_private *ast)
78 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x00);
82 static bool wait_fw_ready(struct ast_private *ast)
87 waitready = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
101 struct ast_private *ast = dev->dev_private;
103 if (wait_nack(ast)) {
104 send_nack(ast);
105 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
106 send_ack(ast);
107 set_cmd_trigger(ast);
109 if (wait_ack(ast)) {
110 clear_cmd_trigger(ast);
111 send_nack(ast);
116 clear_cmd_trigger(ast);
117 send_nack(ast);
123 struct ast_private *ast = dev->dev_private;
125 if (wait_nack(ast)) {
126 send_nack(ast);
127 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
128 send_ack(ast);
129 if (wait_ack(ast)) {
130 send_nack(ast);
134 send_nack(ast);
141 struct ast_private *ast = dev->dev_private;
146 if (wait_ack(ast) == false)
148 tmp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd3, 0xff);
150 if (wait_nack(ast) == false) {
151 send_nack(ast);
154 send_nack(ast);
158 static void clear_cmd(struct ast_private *ast)
160 send_nack(ast);
161 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, 0x00);
173 static u32 get_fw_base(struct ast_private *ast)
175 return ast_mindwm(ast, 0x1e6e2104) & 0x7fffffff;
180 struct ast_private *ast = dev->dev_private;
184 data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
186 boot_address = get_fw_base(ast);
188 *(u32 *)(addr + i) = ast_mindwm(ast, boot_address + i);
196 struct ast_private *ast = dev->dev_private;
202 data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
205 if (ast->dp501_fw_addr) {
206 fw_addr = ast->dp501_fw_addr;
209 if (!ast->dp501_fw &&
213 fw_addr = (u8 *)ast->dp501_fw->data;
214 len = ast->dp501_fw->size;
217 ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8);
218 data = ast_mindwm(ast, 0x1e6e0004);
239 ast_moutdwm(ast, boot_address + i, data);
243 ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8);
246 ast_moutdwm(ast, 0x1e6e2104, 0x80000000 + boot_address);
247 ast_moutdwm(ast, 0x1e6e2100, 1);
250 data = ast_mindwm(ast, 0x1e6e2040) & 0xfffff1ff; /* D[11:9] = 100b: UEFI handling */
252 ast_moutdwm(ast, 0x1e6e2040, data);
254 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xfc); /* D[1:0]: Reserved Video Buffer */
256 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x99, jreg);
263 struct ast_private *ast = dev->dev_private;
267 boot_address = get_fw_base(ast);
271 data = ast_mindwm(ast, boot_address + offset);
277 *(u32 *)linkcap = ast_mindwm(ast, boot_address + offset);
291 struct ast_private *ast = dev->dev_private;
294 boot_address = get_fw_base(ast);
298 data = ast_mindwm(ast, boot_address + offset);
304 data = ast_mindwm(ast, boot_address + offset);
311 data = ast_mindwm(ast, boot_address + offset + i);
320 struct ast_private *ast = dev->dev_private;
323 ast_write32(ast, 0xf004, 0x1e6e0000);
324 ast_write32(ast, 0xf000, 0x1);
325 ast_write32(ast, 0x12000, 0x1688a8a8);
327 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
330 data = ast_read32(ast, 0x12008);
334 ast_write32(ast, 0x12008, data);
336 if (ast->chip == AST2300) {
337 data = ast_read32(ast, 0x12084);
340 ast_write32(ast, 0x12084, data);
342 data = ast_read32(ast, 0x12088);
345 ast_write32(ast, 0x12088, data);
347 data = ast_read32(ast, 0x12090);
351 ast_write32(ast, 0x12090, data);
353 data = ast_read32(ast, 0x12088);
356 ast_write32(ast, 0x12088, data);
358 data = ast_read32(ast, 0x1208c);
361 ast_write32(ast, 0x1208c, data);
363 data = ast_read32(ast, 0x120a4);
366 ast_write32(ast, 0x120a4, data);
368 data = ast_read32(ast, 0x120a8);
371 ast_write32(ast, 0x120a8, data);
373 data = ast_read32(ast, 0x12094);
376 ast_write32(ast, 0x12094, data);
381 data = ast_read32(ast, 0x1202c);
383 ast_write32(ast, 0x1202c, data);
386 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80);
393 struct ast_private *ast = dev->dev_private;
401 ast_write32(ast, 0xf004, 0x1e6e0000);
402 ast_write32(ast, 0xf000, 0x1);
405 ast_write32(ast, 0x12000, 0x1688a8a8);
406 ast_write32(ast, 0x12000, 0x1688a8a8);
407 ast_write32(ast, 0x12000, 0x1688a8a8);
410 data = ast_read32(ast, 0x1202c);
412 ast_write32(ast, 0, data);
415 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x00);
420 struct ast_private *ast = dev->dev_private;
423 if (ast->chip == AST2300 || ast->chip == AST2400) {
424 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
436 if (ast->tx_chip_type == AST_TX_SIL164)
446 struct ast_private *ast = dev->dev_private;
448 release_firmware(ast->dp501_fw);
449 ast->dp501_fw = NULL;
Indexes created Wed Oct 01 13:09:50 GMT 2025