Lines Matching defs:ast
5 * Parts based on xf86-video-ast
61 static void ast_cursor_set_base(struct ast_private *ast, u64 address);
65 static inline void ast_load_palette_index(struct ast_private *ast,
69 ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index);
70 ast_io_read8(ast, AST_IO_SEQ_PORT);
71 ast_io_write8(ast, AST_IO_DAC_DATA, red);
72 ast_io_read8(ast, AST_IO_SEQ_PORT);
73 ast_io_write8(ast, AST_IO_DAC_DATA, green);
74 ast_io_read8(ast, AST_IO_SEQ_PORT);
75 ast_io_write8(ast, AST_IO_DAC_DATA, blue);
76 ast_io_read8(ast, AST_IO_SEQ_PORT);
79 static void ast_crtc_load_lut(struct ast_private *ast, struct drm_crtc *crtc)
92 ast_load_palette_index(ast, i, *r++ >> 8, *g++ >> 8, *b++ >> 8);
217 static void ast_set_vbios_color_reg(struct ast_private *ast,
237 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0x0f) << 4));
239 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
242 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
243 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, format->cpp[0] * 8);
247 static void ast_set_vbios_mode_reg(struct ast_private *ast,
256 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff);
257 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff);
259 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
262 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
263 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000);
264 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay);
265 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8);
266 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay);
267 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8);
271 static void ast_set_std_reg(struct ast_private *ast,
282 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
285 ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03);
286 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x01, 0xdf, stdtable->seq[0]);
289 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg);
293 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
295 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
297 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
299 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
302 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
305 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i);
306 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg);
308 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14);
309 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00);
311 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
312 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20);
316 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]);
319 static void ast_set_crtc_reg(struct ast_private *ast,
326 if ((ast->chip == AST2500) &&
330 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
335 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp);
340 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp);
345 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp);
352 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f));
357 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp);
362 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
364 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC);
365 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD);
375 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp);
384 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp);
391 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf);
400 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp);
409 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp);
414 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp);
416 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07);
417 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09);
418 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80));
421 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80);
423 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00);
425 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80);
428 static void ast_set_offset_reg(struct ast_private *ast,
434 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff));
435 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f);
438 static void ast_set_dclk_reg(struct ast_private *ast,
444 if (ast->chip == AST2500)
449 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
450 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
451 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f,
456 static void ast_set_color_reg(struct ast_private *ast,
480 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0);
481 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3);
482 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
485 static void ast_set_crtthd_reg(struct ast_private *ast)
488 if (ast->chip == AST2300 || ast->chip == AST2400 ||
489 ast->chip == AST2500) {
490 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
491 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
492 } else if (ast->chip == AST2100 ||
493 ast->chip == AST1100 ||
494 ast->chip == AST2200 ||
495 ast->chip == AST2150) {
496 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f);
497 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f);
499 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f);
500 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f);
504 static void ast_set_sync_reg(struct ast_private *ast,
510 jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ);
514 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
517 static void ast_set_start_address_crt1(struct ast_private *ast,
523 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff));
524 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff));
525 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff));
571 struct ast_private *ast = plane->dev->dev_private;
581 ast_set_offset_reg(ast, state->fb);
582 ast_set_start_address_crt1(ast, (u32)gpu_addr);
584 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x00);
591 struct ast_private *ast = plane->dev->dev_private;
593 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20);
628 struct ast_private *ast;
639 ast = crtc->dev->dev_private;
648 dst = drm_gem_vram_vmap(ast->cursor.gbo[ast->cursor.next_index]);
662 drm_gem_vram_vunmap(ast->cursor.gbo[ast->cursor.next_index], dst);
668 drm_gem_vram_vunmap(ast->cursor.gbo[ast->cursor.next_index], dst);
711 struct ast_private *ast = plane->dev->dev_private;
722 gbo = ast->cursor.gbo[ast->cursor.next_index];
726 ast_cursor_set_base(ast, off);
728 ++ast->cursor.next_index;
729 ast->cursor.next_index %= ARRAY_SIZE(ast->cursor.gbo);
737 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg);
744 struct ast_private *ast = plane->dev->dev_private;
746 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00);
772 struct ast_private *ast = crtc->dev->dev_private;
774 if (ast->chip == AST1180)
784 if (ast->tx_chip_type == AST_TX_DP501)
786 ast_crtc_load_lut(ast, crtc);
789 if (ast->tx_chip_type == AST_TX_DP501)
798 struct ast_private *ast = crtc->dev->dev_private;
803 if (ast->chip == AST1180) {
804 DRM_ERROR("AST 1180 modesetting not supported\n");
826 struct ast_private *ast = crtc->dev->dev_private;
828 ast_open_key(ast);
835 struct ast_private *ast = dev->dev_private;
851 ast_set_color_reg(ast, format);
852 ast_set_vbios_color_reg(ast, format, vbios_mode_info);
859 ast_set_vbios_mode_reg(ast, adjusted_mode, vbios_mode_info);
860 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06);
861 ast_set_std_reg(ast, adjusted_mode, vbios_mode_info);
862 ast_set_crtc_reg(ast, adjusted_mode, vbios_mode_info);
863 ast_set_dclk_reg(ast, adjusted_mode, vbios_mode_info);
864 ast_set_crtthd_reg(ast);
865 ast_set_sync_reg(ast, adjusted_mode, vbios_mode_info);
940 struct ast_private *ast = dev->dev_private;
948 ret = drm_crtc_init_with_planes(dev, &crtc->base, &ast->primary_plane,
949 &ast->cursor_plane, &ast_crtc_funcs,
999 struct ast_private *ast = connector->dev->dev_private;
1003 if (ast->tx_chip_type == AST_TX_DP501) {
1004 ast->dp501_maxclk = 0xff;
1011 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev);
1030 struct ast_private *ast = connector->dev->dev_private;
1034 if (ast->support_wide_screen) {
1046 if ((ast->chip == AST2100) || (ast->chip == AST2200) ||
1047 (ast->chip == AST2300) || (ast->chip == AST2400) ||
1048 (ast->chip == AST2500) || (ast->chip == AST1180)) {
1053 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
1144 struct ast_private *ast = dev->dev_private;
1151 for (i = 0; i < ARRAY_SIZE(ast->cursor.gbo); ++i) {
1164 ast->cursor.gbo[i] = gbo;
1172 gbo = ast->cursor.gbo[i];
1175 ast->cursor.gbo[i] = NULL;
1182 struct ast_private *ast = dev->dev_private;
1186 for (i = 0; i < ARRAY_SIZE(ast->cursor.gbo); ++i) {
1187 gbo = ast->cursor.gbo[i];
1195 struct ast_private *ast = dev->dev_private;
1198 memset(&ast->primary_plane, 0, sizeof(ast->primary_plane));
1199 ret = drm_universal_plane_init(dev, &ast->primary_plane, 0x01,
1205 DRM_ERROR("ast: drm_universal_plane_init() failed: %d\n", ret);
1208 drm_plane_helper_add(&ast->primary_plane,
1211 ret = drm_universal_plane_init(dev, &ast->cursor_plane, 0x01,
1220 drm_plane_helper_add(&ast->cursor_plane,
1239 struct ast_private *ast = i2c->dev->dev_private;
1244 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1246 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1251 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1261 struct ast_private *ast = i2c->dev->dev_private;
1266 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1268 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1273 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1283 struct ast_private *ast = i2c->dev->dev_private;
1289 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7);
1290 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01);
1299 struct ast_private *ast = i2c->dev->dev_private;
1305 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7);
1306 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04);
1327 "AST i2c bit bus");
1432 static void ast_cursor_set_base(struct ast_private *ast, u64 address)
1438 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, addr0);
1439 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, addr1);
1440 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, addr2);
1447 struct ast_private *ast = crtc->dev->dev_private;
1453 gbo = ast->cursor.gbo[ast->cursor.next_index];
1473 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset);
1474 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset);
1475 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, (x & 0xff));
1476 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, ((x >> 8) & 0x0f));
1477 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, (y & 0xff));
1478 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07));
1483 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg);
Indexes created Mon Sep 29 21:09:56 GMT 2025