Lines Matching defs:ast
47 struct ast_private *ast = dev->dev_private;
49 ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x01);
50 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, 0x01);
55 struct ast_private *ast = dev->dev_private;
57 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06);
63 struct ast_private *ast = dev->dev_private;
66 if (ast->chip == AST1180) {
69 ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT);
82 struct ast_private *ast = dev->dev_private;
88 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00);
90 if (ast->chip == AST2300 || ast->chip == AST2400 ||
91 ast->chip == AST2500) {
101 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info);
107 /* ast_set_index_reg-mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x3); */
110 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01);
111 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00);
115 if (ast->chip == AST2300 || ast->chip == AST2400 ||
116 ast->chip == AST2500)
118 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
121 u32 ast_mindwm(struct ast_private *ast, u32 r)
125 ast_write32(ast, 0xf004, r & 0xffff0000);
126 ast_write32(ast, 0xf000, 0x1);
129 data = ast_read32(ast, 0xf004) & 0xffff0000;
131 return ast_read32(ast, 0x10000 + (r & 0x0000ffff));
134 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v)
137 ast_write32(ast, 0xf004, r & 0xffff0000);
138 ast_write32(ast, 0xf000, 0x1);
140 data = ast_read32(ast, 0xf004) & 0xffff0000;
142 ast_write32(ast, 0x10000 + (r & 0x0000ffff), v);
173 static u32 mmctestburst2_ast2150(struct ast_private *ast, u32 datagen)
177 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
178 ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3));
181 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
183 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
187 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
188 ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3));
191 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
193 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
197 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
198 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
203 static u32 mmctestsingle2_ast2150(struct ast_private *ast, u32 datagen)
207 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
208 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
211 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
213 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
217 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
218 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
223 static int cbrtest_ast2150(struct ast_private *ast)
228 if (mmctestburst2_ast2150(ast, i))
233 static int cbrscan_ast2150(struct ast_private *ast, int busw)
238 ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]);
240 if (cbrtest_ast2150(ast))
250 static void cbrdlli_ast2150(struct ast_private *ast, int busw)
260 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
261 data = cbrscan_ast2150(ast, busw);
277 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
284 struct ast_private *ast = dev->dev_private;
289 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
292 if (ast->chip == AST2000) {
294 ast_write32(ast, 0xf004, 0x1e6e0000);
295 ast_write32(ast, 0xf000, 0x1);
296 ast_write32(ast, 0x10100, 0xa8);
300 } while (ast_read32(ast, 0x10100) != 0xa8);
302 if (ast->chip == AST2100 || ast->chip == 2200)
307 ast_write32(ast, 0xf004, 0x1e6e0000);
308 ast_write32(ast, 0xf000, 0x1);
309 ast_write32(ast, 0x12000, 0x1688A8A8);
312 } while (ast_read32(ast, 0x12000) != 0x01);
314 ast_write32(ast, 0x10000, 0xfc600309);
317 } while (ast_read32(ast, 0x10000) != 0x01);
324 } else if (dram_reg_info->index == 0x4 && ast->chip != AST2000) {
326 if (ast->dram_type == AST_DRAM_1Gx16)
328 else if (ast->dram_type == AST_DRAM_1Gx32)
331 temp = ast_read32(ast, 0x12070);
334 ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp);
336 ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data);
340 /* AST 2100/2150 DRAM calibration */
341 data = ast_read32(ast, 0x10120);
343 data = ast_read32(ast, 0x10004);
345 cbrdlli_ast2150(ast, 16); /* 16 bits */
347 cbrdlli_ast2150(ast, 32); /* 32 bits */
350 switch (ast->chip) {
352 temp = ast_read32(ast, 0x10140);
353 ast_write32(ast, 0x10140, temp | 0x40);
359 temp = ast_read32(ast, 0x1200c);
360 ast_write32(ast, 0x1200c, temp & 0xfffffffd);
361 temp = ast_read32(ast, 0x12040);
362 ast_write32(ast, 0x12040, temp | 0x40);
371 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
378 struct ast_private *ast = dev->dev_private;
380 pci_read_config_dword(ast->dev->pdev, 0x04, ®);
382 pci_write_config_dword(ast->dev->pdev, 0x04, reg);
385 ast_open_key(ast);
389 if (ast->config_mode == ast_use_p2a) {
390 if (ast->chip == AST2500)
392 else if (ast->chip == AST2300 || ast->chip == AST2400)
399 if (ast->tx_chip_type != AST_TX_NONE)
400 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); /* Enable DVO */
404 /* AST 2300 DRAM settings */
457 static bool mmc_test(struct ast_private *ast, u32 datagen, u8 test_ctl)
461 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
462 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
465 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
469 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
473 ast_moutdwm(ast, 0x1e6e0070, 0x0);
477 static u32 mmc_test2(struct ast_private *ast, u32 datagen, u8 test_ctl)
481 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
482 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
485 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
487 ast_moutdwm(ast, 0x1e6e0070, 0x0);
491 data = ast_mindwm(ast, 0x1e6e0078);
493 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
498 static bool mmc_test_burst(struct ast_private *ast, u32 datagen)
500 return mmc_test(ast, datagen, 0xc1);
503 static u32 mmc_test_burst2(struct ast_private *ast, u32 datagen)
505 return mmc_test2(ast, datagen, 0x41);
508 static bool mmc_test_single(struct ast_private *ast, u32 datagen)
510 return mmc_test(ast, datagen, 0xc5);
513 static u32 mmc_test_single2(struct ast_private *ast, u32 datagen)
515 return mmc_test2(ast, datagen, 0x05);
518 static bool mmc_test_single_2500(struct ast_private *ast, u32 datagen)
520 return mmc_test(ast, datagen, 0x85);
523 static int cbr_test(struct ast_private *ast)
527 data = mmc_test_single2(ast, 0);
531 data = mmc_test_burst2(ast, i);
542 static int cbr_scan(struct ast_private *ast)
548 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
550 if ((data = cbr_test(ast)) != 0) {
563 static u32 cbr_test2(struct ast_private *ast)
567 data = mmc_test_burst2(ast, 0);
570 data |= mmc_test_single2(ast, 0);
577 static u32 cbr_scan2(struct ast_private *ast)
583 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
585 if ((data = cbr_test2(ast)) != 0) {
598 static bool cbr_test3(struct ast_private *ast)
600 if (!mmc_test_burst(ast, 0))
602 if (!mmc_test_single(ast, 0))
607 static bool cbr_scan3(struct ast_private *ast)
612 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
614 if (cbr_test3(ast))
623 static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param)
634 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
635 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
636 data = cbr_scan2(ast);
693 ast_moutdwm(ast, 0x1E6E0080, data);
718 ast_moutdwm(ast, 0x1E6E0084, data);
722 static void finetuneDQSI(struct ast_private *ast)
731 reg_mcr0c = ast_mindwm(ast, 0x1E6E000C);
732 reg_mcr18 = ast_mindwm(ast, 0x1E6E0018);
734 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
749 ast_moutdwm(ast, 0x1E6E000C, 0);
750 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23));
751 ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c);
753 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
754 ast_moutdwm(ast, 0x1E6E0070, 0);
755 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0);
756 if (cbr_scan3(ast)) {
809 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
812 static bool cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param)
817 finetuneDQSI(ast);
818 if (finetuneDQI_L(ast, param) == false)
826 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
827 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
828 data = cbr_scan(ast);
864 ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16));
868 static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *param)
872 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
875 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
889 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
917 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
947 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
977 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
991 ast_moutdwm(ast, 0x1E6E2020, 0x0270);
1005 ast_moutdwm(ast, 0x1E6E2020, 0x0290);
1021 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1039 ast_moutdwm(ast, 0x1E6E2020, 0x02E1);
1057 ast_moutdwm(ast, 0x1E6E2020, 0x0160);
1110 static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
1115 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1116 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1117 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1118 ast_moutdwm(ast, 0x1E6E0034, 0x00000000);
1120 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1121 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1123 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1126 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1127 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1128 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1129 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1130 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1131 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1132 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1133 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1134 ast_moutdwm(ast, 0x1E6E0018, 0x4000A170);
1135 ast_moutdwm(ast, 0x1E6E0018, 0x00002370);
1136 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1137 ast_moutdwm(ast, 0x1E6E0040, 0xFF444444);
1138 ast_moutdwm(ast, 0x1E6E0044, 0x22222222);
1139 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1140 ast_moutdwm(ast, 0x1E6E004C, 0x00000002);
1141 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1142 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1143 ast_moutdwm(ast, 0x1E6E0054, 0);
1144 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1145 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1146 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1147 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1148 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1149 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1152 data = ast_mindwm(ast, 0x1E6E001C);
1154 data = ast_mindwm(ast, 0x1E6E001C);
1157 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1161 ast_moutdwm(ast, 0x1E6E0064, data2);
1167 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1170 ast_moutdwm(ast, 0x1E6E0068, data);
1172 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1174 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1175 ast_moutdwm(ast, 0x1E6E0018, data);
1177 ast_moutdwm(ast, 0x1E6E0018, data);
1179 data = ast_mindwm(ast, 0x1E6E001C);
1182 data = ast_mindwm(ast, 0x1E6E001C);
1185 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff);
1186 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1187 ast_moutdwm(ast, 0x1E6E0018, data);
1189 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1190 ast_moutdwm(ast, 0x1E6E000C, 0x00000040);
1193 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1194 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1195 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1196 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1197 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1198 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1199 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1200 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1201 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1203 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1211 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1214 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1217 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1220 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1221 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1223 data = ast_mindwm(ast, 0x1E6E0070);
1225 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1226 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1227 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1233 static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *param)
1237 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1240 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
1254 ast_moutdwm(ast, 0x1E6E2020, 0x0130);
1269 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
1300 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
1334 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
1367 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
1382 ast_moutdwm(ast, 0x1E6E2020, 0x0261);
1398 ast_moutdwm(ast, 0x1E6E2020, 0x0120);
1414 ast_moutdwm(ast, 0x1E6E2020, 0x02A1);
1430 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1480 static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
1485 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1486 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1487 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1488 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1489 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1491 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1494 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1495 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1496 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1497 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1498 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1499 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1500 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1501 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1502 ast_moutdwm(ast, 0x1E6E0018, 0x4000A130);
1503 ast_moutdwm(ast, 0x1E6E0018, 0x00002330);
1504 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1505 ast_moutdwm(ast, 0x1E6E0040, 0xFF808000);
1506 ast_moutdwm(ast, 0x1E6E0044, 0x88848466);
1507 ast_moutdwm(ast, 0x1E6E0048, 0x44440008);
1508 ast_moutdwm(ast, 0x1E6E004C, 0x00000000);
1509 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1510 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1511 ast_moutdwm(ast, 0x1E6E0054, 0);
1512 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1513 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1514 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1515 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1516 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1517 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1521 data = ast_mindwm(ast, 0x1E6E001C);
1523 data = ast_mindwm(ast, 0x1E6E001C);
1526 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1530 ast_moutdwm(ast, 0x1E6E0064, data2);
1536 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1539 ast_moutdwm(ast, 0x1E6E0068, data);
1541 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1543 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1544 ast_moutdwm(ast, 0x1E6E0018, data);
1546 ast_moutdwm(ast, 0x1E6E0018, data);
1548 data = ast_mindwm(ast, 0x1E6E001C);
1551 data = ast_mindwm(ast, 0x1E6E001C);
1554 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff);
1555 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1556 ast_moutdwm(ast, 0x1E6E0018, data);
1558 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1559 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1562 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1563 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1564 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1565 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1566 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1567 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1569 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1570 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1571 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1572 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
1573 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1574 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1575 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1577 ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
1585 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1586 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1589 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1594 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1595 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1597 data = ast_mindwm(ast, 0x1E6E0070);
1599 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1600 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1601 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1608 struct ast_private *ast = dev->dev_private;
1613 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
1615 ast_write32(ast, 0xf004, 0x1e6e0000);
1616 ast_write32(ast, 0xf000, 0x1);
1617 ast_write32(ast, 0x12000, 0x1688a8a8);
1620 } while (ast_read32(ast, 0x12000) != 0x1);
1622 ast_write32(ast, 0x10000, 0xfc600309);
1625 } while (ast_read32(ast, 0x10000) != 0x1);
1628 temp = ast_read32(ast, 0x12008);
1630 ast_write32(ast, 0x12008, temp);
1634 temp = ast_mindwm(ast, 0x1e6e2070);
1672 get_ddr3_info(ast, ¶m);
1673 ddr3_init(ast, ¶m);
1675 get_ddr2_info(ast, ¶m);
1676 ddr2_init(ast, ¶m);
1679 temp = ast_mindwm(ast, 0x1e6e2040);
1680 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
1685 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
1689 static bool cbr_test_2500(struct ast_private *ast)
1691 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1692 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1693 if (!mmc_test_burst(ast, 0))
1695 if (!mmc_test_single_2500(ast, 0))
1700 static bool ddr_test_2500(struct ast_private *ast)
1702 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1703 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1704 if (!mmc_test_burst(ast, 0))
1706 if (!mmc_test_burst(ast, 1))
1708 if (!mmc_test_burst(ast, 2))
1710 if (!mmc_test_burst(ast, 3))
1712 if (!mmc_test_single_2500(ast, 0))
1717 static void ddr_init_common_2500(struct ast_private *ast)
1719 ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1720 ast_moutdwm(ast, 0x1E6E0008, 0x2003000F);
1721 ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF);
1722 ast_moutdwm(ast, 0x1E6E0040, 0x88448844);
1723 ast_moutdwm(ast, 0x1E6E0044, 0x24422288);
1724 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1725 ast_moutdwm(ast, 0x1E6E004C, 0x22222222);
1726 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1727 ast_moutdwm(ast, 0x1E6E0208, 0x00000000);
1728 ast_moutdwm(ast, 0x1E6E0218, 0x00000000);
1729 ast_moutdwm(ast, 0x1E6E0220, 0x00000000);
1730 ast_moutdwm(ast, 0x1E6E0228, 0x00000000);
1731 ast_moutdwm(ast, 0x1E6E0230, 0x00000000);
1732 ast_moutdwm(ast, 0x1E6E02A8, 0x00000000);
1733 ast_moutdwm(ast, 0x1E6E02B0, 0x00000000);
1734 ast_moutdwm(ast, 0x1E6E0240, 0x86000000);
1735 ast_moutdwm(ast, 0x1E6E0244, 0x00008600);
1736 ast_moutdwm(ast, 0x1E6E0248, 0x80000000);
1737 ast_moutdwm(ast, 0x1E6E024C, 0x80808080);
1740 static void ddr_phy_init_2500(struct ast_private *ast)
1745 ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1748 data = ast_mindwm(ast, 0x1E6E0060) & 0x1;
1753 data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;
1758 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1760 ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1764 ast_moutdwm(ast, 0x1E6E0060, 0x00000006);
1774 static void check_dram_size_2500(struct ast_private *ast, u32 tRFC)
1778 reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;
1779 reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;
1781 ast_moutdwm(ast, 0xA0100000, 0x41424344);
1782 ast_moutdwm(ast, 0x90100000, 0x35363738);
1783 ast_moutdwm(ast, 0x88100000, 0x292A2B2C);
1784 ast_moutdwm(ast, 0x80100000, 0x1D1E1F10);
1787 if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {
1791 } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {
1795 } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {
1801 ast_moutdwm(ast, 0x1E6E0004, reg_04);
1802 ast_moutdwm(ast, 0x1E6E0014, reg_14);
1805 static void enable_cache_2500(struct ast_private *ast)
1809 reg_04 = ast_mindwm(ast, 0x1E6E0004);
1810 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000);
1813 data = ast_mindwm(ast, 0x1E6E0004);
1815 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400);
1818 static void set_mpll_2500(struct ast_private *ast)
1823 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1824 ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1826 ast_moutdwm(ast, addr, 0x0);
1829 ast_moutdwm(ast, 0x1E6E0034, 0x00020000);
1831 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1832 data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;
1836 ast_moutdwm(ast, 0x1E6E2160, 0x00011320);
1841 ast_moutdwm(ast, 0x1E6E2020, param);
1845 static void reset_mmc_2500(struct ast_private *ast)
1847 ast_moutdwm(ast, 0x1E78505C, 0x00000004);
1848 ast_moutdwm(ast, 0x1E785044, 0x00000001);
1849 ast_moutdwm(ast, 0x1E785048, 0x00004755);
1850 ast_moutdwm(ast, 0x1E78504C, 0x00000013);
1852 ast_moutdwm(ast, 0x1E785054, 0x00000077);
1853 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1856 static void ddr3_init_2500(struct ast_private *ast, const u32 *ddr_table)
1859 ast_moutdwm(ast, 0x1E6E0004, 0x00000303);
1860 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1861 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1862 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1863 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
1864 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
1865 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1866 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
1869 ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE);
1870 ast_moutdwm(ast, 0x1E6E0204, 0x00001001);
1871 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1872 ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1873 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1874 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1875 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1876 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1877 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1878 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1879 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1880 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1881 ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1882 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006);
1885 ast_moutdwm(ast, 0x1E6E0034, 0x00020091);
1888 ddr_phy_init_2500(ast);
1890 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1891 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1892 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1894 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1895 enable_cache_2500(ast);
1896 ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1897 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
1900 static void ddr4_init_2500(struct ast_private *ast, const u32 *ddr_table)
1907 ast_moutdwm(ast, 0x1E6E0004, 0x00000313);
1908 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1909 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1910 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1911 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
1912 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
1913 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1914 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
1917 ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE);
1918 ast_moutdwm(ast, 0x1E6E0204, 0x09002000);
1919 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1920 ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1921 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1922 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1923 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1924 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1925 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1926 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1927 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1928 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1929 ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1930 ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C);
1931 ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E);
1934 ast_moutdwm(ast, 0x1E6E0034, 0x0001A991);
1942 ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06);
1944 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1945 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1946 ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8));
1948 ddr_phy_init_2500(ast);
1949 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1950 if (cbr_test_2500(ast)) {
1952 data = ast_mindwm(ast, 0x1E6E03D0);
1965 ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8));
1975 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1976 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1977 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1979 ddr_phy_init_2500(ast);
1980 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1981 if (cbr_test_2500(ast)) {
1992 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1993 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1995 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1998 ddr_phy_init_2500(ast);
2000 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
2001 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
2002 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
2004 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
2005 enable_cache_2500(ast);
2006 ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
2007 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
2010 static bool ast_dram_init_2500(struct ast_private *ast)
2018 set_mpll_2500(ast);
2019 reset_mmc_2500(ast);
2020 ddr_init_common_2500(ast);
2022 data = ast_mindwm(ast, 0x1E6E2070);
2024 ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table);
2026 ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table);
2027 } while (!ddr_test_2500(ast));
2029 ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);
2032 data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;
2033 ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000);
2040 struct ast_private *ast = dev->dev_private;
2044 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
2047 ast_moutdwm(ast, 0x1e600000, 0xAEED1A03);
2048 ast_moutdwm(ast, 0x1e600084, 0x00010000);
2049 ast_moutdwm(ast, 0x1e600088, 0x00000000);
2050 ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
2051 ast_write32(ast, 0xf004, 0x1e6e0000);
2052 ast_write32(ast, 0xf000, 0x1);
2053 ast_write32(ast, 0x12000, 0x1688a8a8);
2054 while (ast_read32(ast, 0x12000) != 0x1)
2057 ast_write32(ast, 0x10000, 0xfc600309);
2058 while (ast_read32(ast, 0x10000) != 0x1)
2062 temp = ast_read32(ast, 0x12008);
2064 ast_write32(ast, 0x12008, temp);
2067 ast_moutdwm(ast, 0x1e6e2090, 0x20000000);
2068 temp = ast_mindwm(ast, 0x1e6e2094);
2070 ast_moutdwm(ast, 0x1e6e2094, temp);
2071 temp = ast_mindwm(ast, 0x1e6e2070);
2073 ast_moutdwm(ast, 0x1e6e207c, 0x00800000);
2075 ast_moutdwm(ast, 0x1e6e2070, 0x00800000);
2078 if (!ast_dram_init_2500(ast))
2081 temp = ast_mindwm(ast, 0x1e6e2040);
2082 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
2087 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
Indexes created Wed Oct 01 07:09:59 GMT 2025