Cross Reference: /src/sys/external/bsd/drm2/dist/drm/drm_dp

Lines Matching refs:dpcd
51  * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
149 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
151 	unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
158 	if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
167 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
169 	unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
284  * drm_dp_dpcd_read() - read a series of bytes from the DPCD
303 	 * HP ZR24w corrupts the first DPCD access after entering power save
311 	 * We just have to do it before any DPCD access and hope that the
334  * drm_dp_dpcd_write() - write a series of bytes to the DPCD
364  * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
384  * @dpcd: DisplayPort configuration data
389 int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
393 	bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
415  * @dpcd: DisplayPort configuration data
420 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
424 	bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
471  * @dpcd: DisplayPort configuration data
478 			     const u8 dpcd[DP_RECEIVER_CAP_SIZE],
481 	bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
489 	bool branch_device = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
538 		clk = drm_dp_downstream_max_clock(dpcd, port_cap);
547 		bpc = drm_dp_downstream_max_bpc(dpcd, port_cap);
658  * to require it. We should query/set the speed via DPCD if supported.
1105  * @psr_cap: PSR capabilities from DPCD
1210 	/* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
1217  * Get a bit mask of DPCD quirks for the sink/branch device identified by
1255  * drm_dp_read_desc - read sink/branch descriptor from DPCD
1257  * @desc: Device decriptor to fill from DPCD
1260  * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the
1295  * @dsc_dpcd: DSC capabilities from DPCD
1298  * Read the slice capabilities DPCD register from DSC sink to get
1353  * @dsc_dpcd: DSC capabilities from DPCD
1355  * Read the DSC DPCD register to parse the line buffer depth in bits which is
1398  * @dsc_dpcd: DSC capabilities from DPCD
1402  * Read the DSC DPCD from the sink device to parse the supported bits per
1410  * Number of input BPC values parsed from the DPCD
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