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Lines Matching defs:we

168  * table type, as we know l4 root entry doesn't have a PSE bit,
230 	/* We take IPS bit as 'PSE' for PTE level. */
444 	 * it also works, so we need to treat root pointer entry
1017 			/* We don't setup 64K shadow entry so far. */
1069 		struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *we)
1076 	GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(we->type)));
1078 	if (we->type == GTT_TYPE_PPGTT_PDE_ENTRY)
1079 		ips = vgpu_ips_enabled(vgpu) && ops->test_ips(we);
1081 	spt = intel_vgpu_find_spt_by_gfn(vgpu, ops->get_pfn(we));
1097 		int type = get_next_pt_type(we->type);
1104 		spt = ppgtt_alloc_spt_gfn(vgpu, type, ops->get_pfn(we), ips);
1128 		     spt, we->val64, we->type);
1140 	/* Because we always split 64KB pages, so clear IPS in shadow PDE. */
1272 		 * controlled by uper PDE. To be simple, we always split
1378 		/* We don't setup 64K shadow entry so far. */
1392 		struct intel_gvt_gtt_entry *we, unsigned long index)
1400 			       we->val64, index);
1403 		    we->type, index, we->val64);
1405 	if (gtt_type_is_pt(get_next_pt_type(we->type))) {
1406 		s = ppgtt_populate_spt_by_guest_entry(vgpu, we);
1412 		ppgtt_generate_shadow_entry(&m, s, we);
1415 		ret = ppgtt_populate_shadow_entry(vgpu, spt, index, we);
1422 		spt, we->val64, we->type);
1598 		struct intel_gvt_gtt_entry *we, unsigned long index)
1607 	new_present = ops->test_present(we);
1617 		ret = ppgtt_handle_guest_entry_add(spt, we, index);
1627 		/* For 64KB splited entries, we need clear them all. */
1653 			spt, we->val64, we->type);
1721 	struct intel_gvt_gtt_entry we, se;
1727 	ppgtt_get_guest_entry(spt, &we, index);
1734 	if (we.type == GTT_TYPE_PPGTT_PTE_64K_ENTRY &&
1742 		ret = ppgtt_handle_guest_write_page_table(spt, &we, index);
1765 		ops->set_entry(spt->guest_page.oos_page->mem, &we, index,
2499 		gvt_err("Why we still has spt not freed?\n");