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Lines Matching refs:dpcd

875 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
881 		dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE;
883 		dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE;
888 		dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE;
889 		dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED;
891 		dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE;
892 		dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED;
894 		dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |=
900 		dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC;
920 	struct intel_vgpu_dpcd_data *dpcd = NULL;
949 	dpcd = port->dpcd;
965 			 * DCPD spec: When a Source Device is writing a DPCD
997 		/* write to virtual DPCD */
998 		if (dpcd && dpcd->data_valid) {
1002 				dpcd->data[p] = buf[t];
1005 					dp_aux_ch_ctl_link_training(dpcd,
1013 				dpcd && dpcd->data_valid);
1023 			 * DPCD spec: A Sink Device receiving a Native AUX CH
1024 			 * read request for an unsupported DPCD address must
1054 		/* read from virtual DPCD to vreg */
1056 		if (dpcd && dpcd->data_valid) {
1060 				t = dpcd->data[addr + i - 1];
1072 				dpcd && dpcd->data_valid);