Lines Matching refs:irq
50 #define get_event_virt_handler(irq, e) (irq->events[e].v_handler)
51 #define get_irq_info(irq, e) (irq->events[e].info)
53 #define irq_to_gvt(irq) \
54 container_of(irq, struct intel_gvt, irq)
155 struct intel_gvt_irq *irq = &gvt->irq;
158 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {
159 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg)
160 return irq->info[i];
184 struct intel_gvt_irq_ops *ops = gvt->irq.ops;
198 * intel_vgpu_reg_master_irq_handler - master IRQ write emulation handler
204 * This function is used to emulate the master IRQ register on gen8+.
214 struct intel_gvt_irq_ops *ops = gvt->irq.ops;
222 * GEN8_MASTER_IRQ is a special irq register,
253 struct intel_gvt_irq_ops *ops = gvt->irq.ops;
327 struct intel_gvt_irq *irq = &vgpu->gvt->irq;
328 struct intel_gvt_irq_map *map = irq->irq_map;
341 for (map = irq->irq_map; map->up_irq_bit != -1; map++) {
346 up_irq_info = irq->info[map->up_irq_group];
348 WARN_ON(up_irq_info != irq->info[map->up_irq_group]);
379 static void init_irq_map(struct intel_gvt_irq *irq)
385 for (map = irq->irq_map; map->up_irq_bit != -1; map++) {
386 up_info = irq->info[map->up_irq_group];
388 down_info = irq->info[map->down_irq_group];
405 static void propagate_event(struct intel_gvt_irq *irq,
412 info = get_irq_info(irq, event);
417 bit = irq->events[event].bit;
428 static void handle_default_event_virt(struct intel_gvt_irq *irq,
431 if (!vgpu->irq.irq_warn_once[event]) {
432 gvt_dbg_core("vgpu%d: IRQ receive event %d (%s)\n",
434 vgpu->irq.irq_warn_once[event] = true;
436 propagate_event(irq, event, vgpu);
444 .name = #regname"-IRQ", \
463 .name = "PCH-IRQ",
471 struct intel_gvt_irq *irq = &vgpu->gvt->irq;
478 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {
479 struct intel_gvt_irq_info *info = irq->info[i];
497 struct intel_gvt_irq *irq)
499 struct intel_gvt *gvt = irq_to_gvt(irq);
515 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_MASTER, &gen8_master_info);
516 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT0, &gen8_gt0_info);
517 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT1, &gen8_gt1_info);
518 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT2, &gen8_gt2_info);
519 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT3, &gen8_gt3_info);
520 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_A, &gen8_de_pipe_a_info);
521 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_B, &gen8_de_pipe_b_info);
522 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_C, &gen8_de_pipe_c_info);
523 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PORT, &gen8_de_port_info);
524 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_MISC, &gen8_de_misc_info);
525 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCU, &gen8_pcu_info);
526 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCH, &gvt_base_pch_info);
531 SET_BIT_INFO(irq, 0, RCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);
532 SET_BIT_INFO(irq, 4, RCS_PIPE_CONTROL, INTEL_GVT_IRQ_INFO_GT0);
533 SET_BIT_INFO(irq, 8, RCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);
535 SET_BIT_INFO(irq, 16, BCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);
536 SET_BIT_INFO(irq, 20, BCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT0);
537 SET_BIT_INFO(irq, 24, BCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);
540 SET_BIT_INFO(irq, 0, VCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT1);
541 SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1);
542 SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1);
545 SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT,
547 SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW,
549 SET_BIT_INFO(irq, 24, VCS2_AS_CONTEXT_SWITCH,
554 SET_BIT_INFO(irq, 0, VECS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT3);
555 SET_BIT_INFO(irq, 4, VECS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT3);
556 SET_BIT_INFO(irq, 8, VECS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT3);
558 SET_BIT_INFO(irq, 0, PIPE_A_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
559 SET_BIT_INFO(irq, 0, PIPE_B_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
560 SET_BIT_INFO(irq, 0, PIPE_C_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
563 SET_BIT_INFO(irq, 0, AUX_CHANNEL_A, INTEL_GVT_IRQ_INFO_DE_PORT);
564 SET_BIT_INFO(irq, 3, DP_A_HOTPLUG, INTEL_GVT_IRQ_INFO_DE_PORT);
567 SET_BIT_INFO(irq, 0, GSE, INTEL_GVT_IRQ_INFO_DE_MISC);
570 SET_BIT_INFO(irq, 17, GMBUS, INTEL_GVT_IRQ_INFO_PCH);
571 SET_BIT_INFO(irq, 19, CRT_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
572 SET_BIT_INFO(irq, 21, DP_B_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
573 SET_BIT_INFO(irq, 22, DP_C_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
574 SET_BIT_INFO(irq, 23, DP_D_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
577 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_PCH);
578 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_PCH);
579 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_PCH);
581 SET_BIT_INFO(irq, 4, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
582 SET_BIT_INFO(irq, 5, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
584 SET_BIT_INFO(irq, 4, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
585 SET_BIT_INFO(irq, 5, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
587 SET_BIT_INFO(irq, 4, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
588 SET_BIT_INFO(irq, 5, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
590 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_DE_PORT);
591 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_DE_PORT);
592 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_DE_PORT);
594 SET_BIT_INFO(irq, 3, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
595 SET_BIT_INFO(irq, 3, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
596 SET_BIT_INFO(irq, 3, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
598 SET_BIT_INFO(irq, 4, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
599 SET_BIT_INFO(irq, 4, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
600 SET_BIT_INFO(irq, 4, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
604 SET_BIT_INFO(irq, 24, PCU_THERMAL, INTEL_GVT_IRQ_INFO_PCU);
605 SET_BIT_INFO(irq, 25, PCU_PCODE2DRIVER_MAILBOX, INTEL_GVT_IRQ_INFO_PCU);
620 * will emulate the IRQ register bit change.
627 struct intel_gvt_irq *irq = &gvt->irq;
629 struct intel_gvt_irq_ops *ops = gvt->irq.ops;
631 handler = get_event_virt_handler(irq, event);
634 handler(irq, event, vgpu);
640 struct intel_gvt_irq *irq)
645 irq->events[i].info = NULL;
646 irq->events[i].v_handler = handle_default_event_virt;
653 struct intel_gvt_irq *irq;
657 irq = container_of(vblank_timer, struct intel_gvt_irq, vblank_timer);
658 gvt = container_of(irq, struct intel_gvt, irq);
666 * intel_gvt_clean_irq - clean up GVT-g IRQ emulation subsystem
669 * This function is called at driver unloading stage, to clean up GVT-g IRQ
675 struct intel_gvt_irq *irq = &gvt->irq;
677 hrtimer_cancel(&irq->vblank_timer.timer);
683 * intel_gvt_init_irq - initialize GVT-g IRQ emulation subsystem
686 * This function is called at driver loading stage, to initialize the GVT-g IRQ
694 struct intel_gvt_irq *irq = &gvt->irq;
695 struct intel_gvt_vblank_timer *vblank_timer = &irq->vblank_timer;
697 gvt_dbg_core("init irq framework\n");
699 irq->ops = &gen8_irq_ops;
700 irq->irq_map = gen8_irq_map;
703 init_events(irq);
706 irq->ops->init_irq(irq);
708 init_irq_map(irq);
Indexes created Wed Oct 22 13:09:56 GMT 2025