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Lines Matching refs:vgpu

56 static void update_upstream_irq(struct intel_vgpu *vgpu,
168  * @vgpu: a vGPU
180 int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu,
183 	struct intel_gvt *gvt = vgpu->gvt;
187 	trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg),
188 		       (vgpu_vreg(vgpu, reg) ^ imr));
190 	vgpu_vreg(vgpu, reg) = imr;
192 	ops->check_pending_irq(vgpu);
199  * @vgpu: a vGPU
210 int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu,
213 	struct intel_gvt *gvt = vgpu->gvt;
216 	u32 virtual_ier = vgpu_vreg(vgpu, reg);
218 	trace_write_ir(vgpu->id, "MASTER_IRQ", reg, ier, virtual_ier,
228 	vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL;
229 	vgpu_vreg(vgpu, reg) |= ier;
231 	ops->check_pending_irq(vgpu);
238  * @vgpu: a vGPU
249 int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
252 	struct intel_gvt *gvt = vgpu->gvt;
257 	trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg),
258 		       (vgpu_vreg(vgpu, reg) ^ ier));
260 	vgpu_vreg(vgpu, reg) = ier;
267 		update_upstream_irq(vgpu, info);
269 	ops->check_pending_irq(vgpu);
276  * @vgpu: a vGPU
287 int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
290 	struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt,
294 	trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),
295 		       (vgpu_vreg(vgpu, reg) ^ iir));
300 	vgpu_vreg(vgpu, reg) &= ~iir;
303 		update_upstream_irq(vgpu, info);
324 static void update_upstream_irq(struct intel_vgpu *vgpu,
327 	struct intel_gvt_irq *irq = &vgpu->gvt->irq;
333 	u32 val = vgpu_vreg(vgpu,
335 		& vgpu_vreg(vgpu,
364 		vgpu_vreg(vgpu, isr) &= ~clear_bits;
365 		vgpu_vreg(vgpu, isr) |= set_bits;
372 		vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr));
376 		update_upstream_irq(vgpu, up_irq_info);
400 static int inject_virtual_interrupt(struct intel_vgpu *vgpu)
402 	return intel_gvt_hypervisor_inject_msi(vgpu);
406 	enum intel_gvt_event_type event, struct intel_vgpu *vgpu)
419 	if (!test_bit(bit, (void *)&vgpu_vreg(vgpu,
421 		trace_propagate_event(vgpu->id, irq_name[event], bit);
422 		set_bit(bit, (void *)&vgpu_vreg(vgpu,
429 	enum intel_gvt_event_type event, struct intel_vgpu *vgpu)
431 	if (!vgpu->irq.irq_warn_once[event]) {
432 		gvt_dbg_core("vgpu%d: IRQ receive event %d (%s)\n",
433 			vgpu->id, event, irq_name[event]);
434 		vgpu->irq.irq_warn_once[event] = true;
436 	propagate_event(irq, event, vgpu);
469 static void gen8_check_pending_irq(struct intel_vgpu *vgpu)
471 	struct intel_gvt_irq *irq = &vgpu->gvt->irq;
474 	if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &
486 		if ((vgpu_vreg(vgpu, regbase_to_iir(reg_base))
487 				& vgpu_vreg(vgpu, regbase_to_ier(reg_base))))
488 			update_upstream_irq(vgpu, info);
491 	if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ))
493 		inject_virtual_interrupt(vgpu);
614  * intel_vgpu_trigger_virtual_event - Trigger a virtual event for a vGPU
615  * @vgpu: a vGPU
618  * This function is used to trigger a virtual interrupt event for vGPU.
623 void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu,
626 	struct intel_gvt *gvt = vgpu->gvt;
634 	handler(irq, event, vgpu);
636 	ops->check_pending_irq(vgpu);