Cross Reference: /src/sys/external/bsd/drm2/dist/drm/i915/gvt/mmio.c

Lines Matching refs:vgpu
46  * @vgpu: a vGPU
52 int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa)
54 	u64 gttmmio_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0);
65 static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, u64 pa,
72 	if (!vgpu || !p_data)
75 	gvt = vgpu->gvt;
76 	mutex_lock(&vgpu->vgpu_lock);
77 	offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
80 			intel_vgpu_default_mmio_read(vgpu, offset, p_data,
83 			intel_vgpu_default_mmio_write(vgpu, offset, p_data,
87 		pt = vgpu->gtt.ggtt_mm->ggtt_mm.virtual_ggtt + offset;
94 	mutex_unlock(&vgpu->vgpu_lock);
99  * @vgpu: a vGPU
107 int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
110 	struct intel_gvt *gvt = vgpu->gvt;
114 	if (vgpu->failsafe) {
115 		failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, true);
118 	mutex_lock(&vgpu->vgpu_lock);
120 	offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
133 		ret = intel_vgpu_emulate_ggtt_mmio_read(vgpu, offset,
141 		ret = intel_gvt_hypervisor_read_gpa(vgpu, pa, p_data, bytes);
153 	ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, true);
165 	mutex_unlock(&vgpu->vgpu_lock);
171  * @vgpu: a vGPU
179 int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
182 	struct intel_gvt *gvt = vgpu->gvt;
186 	if (vgpu->failsafe) {
187 		failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, false);
191 	mutex_lock(&vgpu->vgpu_lock);
193 	offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
206 		ret = intel_vgpu_emulate_ggtt_mmio_write(vgpu, offset,
214 		ret = intel_gvt_hypervisor_write_gpa(vgpu, pa, p_data, bytes);
218 	ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false);
229 	mutex_unlock(&vgpu->vgpu_lock);
236  * @vgpu: a vGPU
239 void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
241 	struct intel_gvt *gvt = vgpu->gvt;
246 		memcpy(vgpu->mmio.vreg, mmio, info->mmio_size);
248 		vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;
251 		vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0;
253 		if (IS_BROXTON(vgpu->gvt->dev_priv)) {
254 			vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &=
256 			vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
258 			vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
260 			vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &=
262 			vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &=
264 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
266 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
269 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
271 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
274 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
276 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
286 		memcpy(vgpu->mmio.vreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
293  * @vgpu: a vGPU
298 int intel_vgpu_init_mmio(struct intel_vgpu *vgpu)
300 	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
302 	vgpu->mmio.vreg = vzalloc(info->mmio_size);
303 	if (!vgpu->mmio.vreg)
306 	intel_vgpu_reset_mmio(vgpu, true);
313  * @vgpu: a vGPU
316 void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu)
318 	vfree(vgpu->mmio.vreg);
319 	vgpu->mmio.vreg = NULL;
OpenGrok
