Lines Matching defs:iir
178 i915_reg_t iir, i915_reg_t ier)
185 /* IIR can theoretically queue up two events. Be paranoid. */
186 intel_uncore_write(uncore, iir, 0xffffffff);
187 intel_uncore_posting_read(uncore, iir);
188 intel_uncore_write(uncore, iir, 0xffffffff);
189 intel_uncore_posting_read(uncore, iir);
199 /* IIR can theoretically queue up two events. Be paranoid. */
242 i915_reg_t iir)
244 gen3_assert_iir_is_zero(uncore, iir);
1301 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1339 if (iir & iir_bit)
1350 * Clear the PIPE*STAT regs before the IIR
1355 * triggered IIR on i965/g4x wouldn't notice that
1367 u16 iir, u32 pipe_stats[I915_MAX_PIPES])
1384 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1403 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1408 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1427 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1470 * edge triggered IIR will not notice that an interrupt
1537 u32 iir, gt_iir, pm_iir;
1544 iir = I915_READ(VLV_IIR);
1546 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1573 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1577 * signalled in iir */
1578 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1580 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1588 if (iir)
1589 I915_WRITE(VLV_IIR, iir);
1622 u32 master_ctl, iir;
1629 iir = I915_READ(VLV_IIR);
1631 if (master_ctl == 0 && iir == 0)
1655 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1659 * signalled in iir */
1660 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1662 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1671 if (iir)
1672 I915_WRITE(VLV_IIR, iir);
1753 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1836 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2049 * 3 - Clear the Interrupt Identity bits (IIR).
2065 /* disable master interrupt before clearing iir */
2136 static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2139 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
2140 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
2175 DRM_ERROR("Unexpected DE HPD interrupt 0x%08x\n", iir);
2220 gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2224 if (iir & GEN8_DE_MISC_GSE) {
2229 if (iir & GEN8_DE_EDP_PSR) {
2255 u32 iir;
2259 iir = I915_READ(GEN8_DE_MISC_IIR);
2260 if (iir) {
2261 I915_WRITE(GEN8_DE_MISC_IIR, iir);
2263 gen8_de_misc_irq_handler(dev_priv, iir);
2270 iir = I915_READ(GEN11_DE_HPD_IIR);
2271 if (iir) {
2272 I915_WRITE(GEN11_DE_HPD_IIR, iir);
2274 gen11_hpd_irq_handler(dev_priv, iir);
2281 iir = I915_READ(GEN8_DE_PORT_IIR);
2282 if (iir) {
2286 I915_WRITE(GEN8_DE_PORT_IIR, iir);
2289 if (iir & gen8_de_port_aux_mask(dev_priv)) {
2295 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2302 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2310 if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2328 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2329 if (!iir) {
2335 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2337 if (iir & GEN8_PIPE_VBLANK)
2340 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2343 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2346 fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
2360 iir = I915_READ(SDEIIR);
2361 if (iir) {
2362 I915_WRITE(SDEIIR, iir);
2366 icp_irq_handler(dev_priv, iir);
2368 spt_irq_handler(dev_priv, iir);
2370 cpt_irq_handler(dev_priv, iir);
2436 u32 iir;
2441 iir = raw_reg_read(gt->uncore, GEN11_GU_MISC_IIR);
2442 if (likely(iir))
2443 raw_reg_write(gt->uncore, GEN11_GU_MISC_IIR, iir);
2445 return iir;
2449 gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
2451 if (iir & GEN11_GU_MISC_GSE)
3548 * IIR on i965/g4x wouldn't notice that an interrupt
3585 * IIR on i965/g4x wouldn't notice that an interrupt
3619 u16 iir;
3621 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);
3622 if (iir == 0)
3628 * signalled in iir */
3629 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
3631 if (iir & I915_MASTER_ERROR_INTERRUPT)
3634 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);
3636 if (iir & I915_USER_INTERRUPT)
3639 if (iir & I915_MASTER_ERROR_INTERRUPT)
3642 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
3720 u32 iir;
3722 iir = I915_READ(GEN2_IIR);
3723 if (iir == 0)
3729 iir & I915_DISPLAY_PORT_INTERRUPT)
3733 * signalled in iir */
3734 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
3736 if (iir & I915_MASTER_ERROR_INTERRUPT)
3739 I915_WRITE(GEN2_IIR, iir);
3741 if (iir & I915_USER_INTERRUPT)
3744 if (iir & I915_MASTER_ERROR_INTERRUPT)
3750 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
3863 u32 iir;
3865 iir = I915_READ(GEN2_IIR);
3866 if (iir == 0)
3871 if (iir & I915_DISPLAY_PORT_INTERRUPT)
3875 * signalled in iir */
3876 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
3878 if (iir & I915_MASTER_ERROR_INTERRUPT)
3881 I915_WRITE(GEN2_IIR, iir);
3883 if (iir & I915_USER_INTERRUPT)
3886 if (iir & I915_BSD_USER_INTERRUPT)
3889 if (iir & I915_MASTER_ERROR_INTERRUPT)
3895 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
Indexes created Thu Oct 02 14:10:14 GMT 2025